2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * Declaration of a memory trace CPU object. Uses a memory trace to drive the
32 * provided memory hierarchy.
35 #include <algorithm> // For min
37 #include "cpu/trace/trace_cpu.hh"
38 #include "cpu/trace/reader/mem_trace_reader.hh"
39 #include "mem/base_mem.hh" // For PARAM constructor
40 #include "mem/mem_interface.hh"
41 #include "sim/builder.hh"
42 #include "sim/sim_events.hh"
46 TraceCPU::TraceCPU(const string
&name
,
47 MemInterface
*icache_interface
,
48 MemInterface
*dcache_interface
,
49 MemTraceReader
*data_trace
)
50 : BaseCPU(name
, 4), icacheInterface(icache_interface
),
51 dcacheInterface(dcache_interface
),
52 dataTrace(data_trace
), outstandingRequests(0), tickEvent(this)
54 assert(dcacheInterface
);
55 nextCycle
= dataTrace
->getNextReq(nextReq
);
56 tickEvent
.schedule(0);
62 assert(outstandingRequests
>= 0);
63 assert(outstandingRequests
< 1000);
67 while (nextReq
&& curTick
>= nextCycle
) {
68 assert(nextReq
->thread_num
< 4 && "Not enough threads");
69 if (nextReq
->isInstRead() && icacheInterface
) {
70 if (icacheInterface
->isBlocked())
73 nextReq
->time
= curTick
;
74 if (nextReq
->cmd
== Squash
) {
75 icacheInterface
->squash(nextReq
->asid
);
78 nextReq
->completionEvent
=
79 new TraceCompleteEvent(nextReq
, this);
80 icacheInterface
->access(nextReq
);
83 if (dcacheInterface
->isBlocked())
87 nextReq
->time
= curTick
;
88 nextReq
->completionEvent
=
89 new TraceCompleteEvent(nextReq
, this);
90 dcacheInterface
->access(nextReq
);
92 nextCycle
= dataTrace
->getNextReq(nextReq
);
96 // No more requests to send. Finish trailing events and exit.
97 if (mainEventQueue
.empty()) {
98 new SimExitEvent("Finshed Memory Trace");
100 tickEvent
.schedule(mainEventQueue
.nextEventTime() + 1);
103 tickEvent
.schedule(max(curTick
+ 1, nextCycle
));
108 TraceCPU::completeRequest(MemReqPtr
& req
)
113 TraceCompleteEvent::process()
115 tester
->completeRequest(req
);
119 TraceCompleteEvent::description()
121 return "trace access complete";
124 TraceCPU::TickEvent::TickEvent(TraceCPU
*c
)
125 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
130 TraceCPU::TickEvent::process()
136 TraceCPU::TickEvent::description()
138 return "TraceCPU tick event";
143 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
145 SimObjectParam
<BaseMem
*> icache
;
146 SimObjectParam
<BaseMem
*> dcache
;
147 SimObjectParam
<MemTraceReader
*> data_trace
;
149 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
151 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
153 INIT_PARAM_DFLT(icache
, "instruction cache", NULL
),
154 INIT_PARAM_DFLT(dcache
, "data cache", NULL
),
155 INIT_PARAM_DFLT(data_trace
, "data trace", NULL
)
157 END_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
159 CREATE_SIM_OBJECT(TraceCPU
)
161 return new TraceCPU(getInstanceName(),
162 (icache
) ? icache
->getInterface() : NULL
,
163 (dcache
) ? dcache
->getInterface() : NULL
,
167 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU
)