cpu/trace/trace_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of a memory trace CPU object. Uses a memory trace to drive the
  32  * provided memory hierarchy.
  33  */
  34
  35 #include <algorithm> // For min
  36
  37 #include "cpu/trace/trace_cpu.hh"
  38 #include "cpu/trace/reader/mem_trace_reader.hh"
  39 #include "mem/base_mem.hh" // For PARAM constructor
  40 #include "mem/mem_interface.hh"
  41 #include "sim/builder.hh"
  42 #include "sim/sim_events.hh"
  43
  44 using namespace std;
  45
  46 TraceCPU::TraceCPU(const string &name,
  47                    MemInterface *icache_interface,
  48                    MemInterface *dcache_interface,
  49                    MemTraceReader *inst_trace,
  50                    MemTraceReader *data_trace,
  51                    int icache_ports,
  52                    int dcache_ports)
  53     : BaseCPU(name, 4), icacheInterface(icache_interface),
  54       dcacheInterface(dcache_interface), instTrace(inst_trace),
  55       dataTrace(data_trace), icachePorts(icache_ports),
  56       dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
  57 {
  58     if (instTrace) {
  59         assert(icacheInterface);
  60         nextInstCycle = instTrace->getNextReq(nextInstReq);
  61     }
  62     if (dataTrace) {
  63         assert(dcacheInterface);
  64         nextDataCycle = dataTrace->getNextReq(nextDataReq);
  65     }
  66     tickEvent.schedule(0);
  67 }
  68
  69 void
  70 TraceCPU::tick()
  71 {
  72     assert(outstandingRequests >= 0);
  73     assert(outstandingRequests < 1000);
  74     int instReqs = 0;
  75     int dataReqs = 0;
  76
  77     // Do data first to match tracing with FullCPU dumps
  78
  79     while (nextDataReq && (dataReqs < dcachePorts) &&
  80            curTick >= nextDataCycle) {
  81         assert(nextDataReq->thread_num < 4 && "Not enough threads");
  82         if (dcacheInterface->isBlocked())
  83             break;
  84
  85         ++dataReqs;
  86         nextDataReq->time = curTick;
  87         nextDataReq->completionEvent =
  88             new TraceCompleteEvent(nextDataReq, this);
  89         dcacheInterface->access(nextDataReq);
  90         nextDataCycle = dataTrace->getNextReq(nextDataReq);
  91     }
  92
  93     while (nextInstReq && (instReqs < icachePorts) &&
  94            curTick >= nextInstCycle) {
  95         assert(nextInstReq->thread_num < 4 && "Not enough threads");
  96         if (icacheInterface->isBlocked())
  97             break;
  98
  99         nextInstReq->time = curTick;
 100         if (nextInstReq->cmd == Squash) {
 101             icacheInterface->squash(nextInstReq->asid);
 102         } else {
 103             ++instReqs;
 104             nextInstReq->completionEvent =
 105                 new TraceCompleteEvent(nextInstReq, this);
 106             icacheInterface->access(nextInstReq);
 107         }
 108         nextInstCycle = instTrace->getNextReq(nextInstReq);
 109     }
 110
 111     if (!nextInstReq && !nextDataReq) {
 112         // No more requests to send. Finish trailing events and exit.
 113         if (mainEventQueue.empty()) {
 114             new SimExitEvent("Finshed Memory Trace");
 115         } else {
 116             tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
 117         }
 118     } else {
 119         tickEvent.schedule(max(curTick + 1,
 120                                min(nextInstCycle, nextDataCycle)));
 121     }
 122 }
 123
 124 void
 125 TraceCPU::completeRequest(MemReqPtr& req)
 126 {
 127 }
 128
 129 void
 130 TraceCompleteEvent::process()
 131 {
 132     tester->completeRequest(req);
 133 }
 134
 135 const char *
 136 TraceCompleteEvent::description()
 137 {
 138     return "trace access complete";
 139 }
 140
 141 TraceCPU::TickEvent::TickEvent(TraceCPU *c)
 142     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
 143 {
 144 }
 145
 146 void
 147 TraceCPU::TickEvent::process()
 148 {
 149     cpu->tick();
 150 }
 151
 152 const char *
 153 TraceCPU::TickEvent::description()
 154 {
 155     return "TraceCPU tick event";
 156 }
 157
 158
 159
 160 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 161
 162     SimObjectParam<BaseMem *> icache;
 163     SimObjectParam<BaseMem *> dcache;
 164     SimObjectParam<MemTraceReader *> inst_trace;
 165     SimObjectParam<MemTraceReader *> data_trace;
 166     Param<int> inst_ports;
 167     Param<int> data_ports;
 168
 169 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 170
 171 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 172
 173     INIT_PARAM_DFLT(icache, "instruction cache", NULL),
 174     INIT_PARAM_DFLT(dcache, "data cache", NULL),
 175     INIT_PARAM_DFLT(inst_trace, "instruction trace", NULL),
 176     INIT_PARAM_DFLT(data_trace, "data trace", NULL),
 177     INIT_PARAM_DFLT(inst_ports, "instruction cache read ports", 4),
 178     INIT_PARAM_DFLT(data_ports, "data cache read/write ports", 4)
 179
 180 END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 181
 182 CREATE_SIM_OBJECT(TraceCPU)
 183 {
 184     return new TraceCPU(getInstanceName(),
 185                         (icache) ? icache->getInterface() : NULL,
 186                         (dcache) ? dcache->getInterface() : NULL,
 187                         inst_trace, data_trace, inst_ports, data_ports);
 188 }
 189
 190 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
 191