2 * Copyright (c) 2003 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * Declaration of a memory trace CPU object. Uses a memory trace to drive the
32 * provided memory hierarchy.
35 #include <algorithm> // For min
37 #include "cpu/trace/trace_cpu.hh"
38 #include "cpu/trace/reader/mem_trace_reader.hh"
39 #include "mem/base_mem.hh" // For PARAM constructor
40 #include "mem/mem_interface.hh"
41 #include "sim/builder.hh"
42 #include "sim/sim_events.hh"
46 TraceCPU::TraceCPU(const string
&name
,
47 MemInterface
*icache_interface
,
48 MemInterface
*dcache_interface
,
49 MemTraceReader
*inst_trace
,
50 MemTraceReader
*data_trace
,
53 : BaseCPU(name
, 4), icacheInterface(icache_interface
),
54 dcacheInterface(dcache_interface
), instTrace(inst_trace
),
55 dataTrace(data_trace
), icachePorts(icache_ports
),
56 dcachePorts(dcache_ports
), outstandingRequests(0), tickEvent(this)
59 assert(icacheInterface
);
60 nextInstCycle
= instTrace
->getNextReq(nextInstReq
);
63 assert(dcacheInterface
);
64 nextDataCycle
= dataTrace
->getNextReq(nextDataReq
);
66 tickEvent
.schedule(0);
72 assert(outstandingRequests
>= 0);
73 assert(outstandingRequests
< 1000);
77 // Do data first to match tracing with FullCPU dumps
79 while (nextDataReq
&& (dataReqs
< dcachePorts
) &&
80 curTick
>= nextDataCycle
) {
81 assert(nextDataReq
->thread_num
< 4 && "Not enough threads");
82 if (dcacheInterface
->isBlocked())
86 nextDataReq
->time
= curTick
;
87 nextDataReq
->completionEvent
=
88 new TraceCompleteEvent(nextDataReq
, this);
89 dcacheInterface
->access(nextDataReq
);
90 nextDataCycle
= dataTrace
->getNextReq(nextDataReq
);
93 while (nextInstReq
&& (instReqs
< icachePorts
) &&
94 curTick
>= nextInstCycle
) {
95 assert(nextInstReq
->thread_num
< 4 && "Not enough threads");
96 if (icacheInterface
->isBlocked())
99 nextInstReq
->time
= curTick
;
100 if (nextInstReq
->cmd
== Squash
) {
101 icacheInterface
->squash(nextInstReq
->asid
);
104 nextInstReq
->completionEvent
=
105 new TraceCompleteEvent(nextInstReq
, this);
106 icacheInterface
->access(nextInstReq
);
108 nextInstCycle
= instTrace
->getNextReq(nextInstReq
);
111 if (!nextInstReq
&& !nextDataReq
) {
112 // No more requests to send. Finish trailing events and exit.
113 if (mainEventQueue
.empty()) {
114 new SimExitEvent("Finshed Memory Trace");
116 tickEvent
.schedule(mainEventQueue
.nextEventTime() + 1);
119 tickEvent
.schedule(max(curTick
+ 1,
120 min(nextInstCycle
, nextDataCycle
)));
125 TraceCPU::completeRequest(MemReqPtr
& req
)
130 TraceCompleteEvent::process()
132 tester
->completeRequest(req
);
136 TraceCompleteEvent::description()
138 return "trace access complete";
141 TraceCPU::TickEvent::TickEvent(TraceCPU
*c
)
142 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
147 TraceCPU::TickEvent::process()
153 TraceCPU::TickEvent::description()
155 return "TraceCPU tick event";
160 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
162 SimObjectParam
<BaseMem
*> icache
;
163 SimObjectParam
<BaseMem
*> dcache
;
164 SimObjectParam
<MemTraceReader
*> inst_trace
;
165 SimObjectParam
<MemTraceReader
*> data_trace
;
166 Param
<int> inst_ports
;
167 Param
<int> data_ports
;
169 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU
)
171 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
173 INIT_PARAM_DFLT(icache
, "instruction cache", NULL
),
174 INIT_PARAM_DFLT(dcache
, "data cache", NULL
),
175 INIT_PARAM_DFLT(inst_trace
, "instruction trace", NULL
),
176 INIT_PARAM_DFLT(data_trace
, "data trace", NULL
),
177 INIT_PARAM_DFLT(inst_ports
, "instruction cache read ports", 4),
178 INIT_PARAM_DFLT(data_ports
, "data cache read/write ports", 4)
180 END_INIT_SIM_OBJECT_PARAMS(TraceCPU
)
182 CREATE_SIM_OBJECT(TraceCPU
)
184 return new TraceCPU(getInstanceName(),
185 (icache
) ? icache
->getInterface() : NULL
,
186 (dcache
) ? dcache
->getInterface() : NULL
,
187 inst_trace
, data_trace
, inst_ports
, data_ports
);
190 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU
)