cpu/trace/trace_cpu.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of a memory trace CPU object. Uses a memory trace to drive the
  32  * provided memory hierarchy.
  33  */
  34
  35 #include <algorithm> // For min
  36
  37 #include "cpu/trace/trace_cpu.hh"
  38 #include "cpu/trace/reader/mem_trace_reader.hh"
  39 #include "mem/base_mem.hh" // For PARAM constructor
  40 #include "mem/mem_interface.hh"
  41 #include "sim/builder.hh"
  42 #include "sim/sim_events.hh"
  43
  44 using namespace std;
  45
  46 TraceCPU::TraceCPU(const string &name,
  47                    MemInterface *icache_interface,
  48                    MemInterface *dcache_interface,
  49                    MemTraceReader *data_trace)
  50     : BaseCPU(name, 4), icacheInterface(icache_interface),
  51       dcacheInterface(dcache_interface),
  52       dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
  53 {
  54     assert(dcacheInterface);
  55     nextCycle = dataTrace->getNextReq(nextReq);
  56     tickEvent.schedule(0);
  57 }
  58
  59 void
  60 TraceCPU::tick()
  61 {
  62     assert(outstandingRequests >= 0);
  63     assert(outstandingRequests < 1000);
  64     int instReqs = 0;
  65     int dataReqs = 0;
  66
  67     while (nextReq && curTick >= nextCycle) {
  68         assert(nextReq->thread_num < 4 && "Not enough threads");
  69         if (nextReq->isInstRead() && icacheInterface) {
  70             if (icacheInterface->isBlocked())
  71                 break;
  72
  73             nextReq->time = curTick;
  74             if (nextReq->cmd == Squash) {
  75                 icacheInterface->squash(nextReq->asid);
  76             } else {
  77                 ++instReqs;
  78                 nextReq->completionEvent =
  79                     new TraceCompleteEvent(nextReq, this);
  80                 icacheInterface->access(nextReq);
  81             }
  82         } else {
  83             if (dcacheInterface->isBlocked())
  84                 break;
  85
  86             ++dataReqs;
  87             nextReq->time = curTick;
  88             nextReq->completionEvent =
  89                 new TraceCompleteEvent(nextReq, this);
  90             dcacheInterface->access(nextReq);
  91         }
  92         nextCycle = dataTrace->getNextReq(nextReq);
  93     }
  94
  95     if (!nextReq) {
  96         // No more requests to send. Finish trailing events and exit.
  97         if (mainEventQueue.empty()) {
  98             new SimExitEvent("Finshed Memory Trace");
  99         } else {
 100             tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
 101         }
 102     } else {
 103         tickEvent.schedule(max(curTick + 1, nextCycle));
 104     }
 105 }
 106
 107 void
 108 TraceCPU::completeRequest(MemReqPtr& req)
 109 {
 110 }
 111
 112 void
 113 TraceCompleteEvent::process()
 114 {
 115     tester->completeRequest(req);
 116 }
 117
 118 const char *
 119 TraceCompleteEvent::description()
 120 {
 121     return "trace access complete";
 122 }
 123
 124 TraceCPU::TickEvent::TickEvent(TraceCPU *c)
 125     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
 126 {
 127 }
 128
 129 void
 130 TraceCPU::TickEvent::process()
 131 {
 132     cpu->tick();
 133 }
 134
 135 const char *
 136 TraceCPU::TickEvent::description()
 137 {
 138     return "TraceCPU tick event";
 139 }
 140
 141
 142
 143 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 144
 145     SimObjectParam<BaseMem *> icache;
 146     SimObjectParam<BaseMem *> dcache;
 147     SimObjectParam<MemTraceReader *> data_trace;
 148
 149 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 150
 151 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 152
 153     INIT_PARAM_DFLT(icache, "instruction cache", NULL),
 154     INIT_PARAM_DFLT(dcache, "data cache", NULL),
 155     INIT_PARAM_DFLT(data_trace, "data trace", NULL)
 156
 157 END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 158
 159 CREATE_SIM_OBJECT(TraceCPU)
 160 {
 161     return new TraceCPU(getInstanceName(),
 162                         (icache) ? icache->getInterface() : NULL,
 163                         (dcache) ? dcache->getInterface() : NULL,
 164                         data_trace);
 165 }
 166
 167 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
 168