cpu/trace/trace_cpu.hh

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of a memory trace CPU object. Uses a memory trace to drive the
  32  * provided memory hierarchy.
  33  */
  34
  35 #ifndef __TRACE_CPU_HH__
  36 #define __TRACE_CPU_HH__
  37
  38 #include <string>
  39
  40 #include "cpu/base_cpu.hh"
  41 #include "mem/mem_req.hh" // for MemReqPtr
  42 #include "sim/eventq.hh" // for Event
  43
  44 // Forward declaration.
  45 class MemInterface;
  46 class MemTraceReader;
  47
  48 /**
  49  * A cpu object for running memory traces through a memory hierarchy.
  50  */
  51 class TraceCPU : public BaseCPU
  52 {
  53     /** Interface for instruction trace requests, if any. */
  54     MemInterface *icacheInterface;
  55     /** Interface for data trace requests, if any. */
  56     MemInterface *dcacheInterface;
  57
  58     /** Instruction reference trace. */
  59     MemTraceReader *instTrace;
  60     /** Data reference trace. */
  61     MemTraceReader *dataTrace;
  62
  63     /** Number of Icache read ports. */
  64     int icachePorts;
  65     /** Number of Dcache read/write ports. */
  66     int dcachePorts;
  67
  68     /** Number of outstanding requests. */
  69     int outstandingRequests;
  70
  71     /** Cycle of the next instruction request, 0 if not available. */
  72     Tick nextInstCycle;
  73     /** Cycle of the next data request, 0 if not available. */
  74     Tick nextDataCycle;
  75
  76     /** Next instruction request. */
  77     MemReqPtr nextInstReq;
  78     /** Next data request. */
  79     MemReqPtr nextDataReq;
  80
  81     /**
  82      * Event to call the TraceCPU::tick
  83      */
  84     class TickEvent : public Event
  85     {
  86       private:
  87         /** The associated CPU */
  88         TraceCPU *cpu;
  89
  90       public:
  91         /**
  92          * Construct this event;
  93          */
  94         TickEvent(TraceCPU *c);
  95
  96         /**
  97          * Call the tick function.
  98          */
  99         void process();
 100
 101         /**
 102          * Return a string description of this event.
 103          */
 104         const char *description();
 105     };
 106
 107     TickEvent tickEvent;
 108
 109   public:
 110     /**
 111      * Construct a TraceCPU object.
 112      */
 113     TraceCPU(const std::string &name,
 114              MemInterface *icache_interface,
 115              MemInterface *dcache_interface,
 116              MemTraceReader *inst_trace,
 117              MemTraceReader *data_trace,
 118              int icache_ports,
 119              int dcache_ports);
 120
 121     /**
 122      * Perform all the accesses for one cycle.
 123      */
 124     void tick();
 125
 126     /**
 127      * Handle a completed memory request.
 128      */
 129     void completeRequest(MemReqPtr &req);
 130 };
 131
 132 class TraceCompleteEvent : public Event
 133 {
 134     MemReqPtr req;
 135     TraceCPU *tester;
 136
 137   public:
 138
 139     TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester)
 140         : Event(&mainEventQueue), req(_req), tester(_tester)
 141     {
 142         setFlags(AutoDelete);
 143     }
 144
 145     void process();
 146
 147     virtual const char *description();
 148 };
 149
 150 #endif //__TRACE_CPU_HH__
 151