3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
62 def __init__(self
, comb
, sync
):
65 self
.mpie
= Signal(name
="mstatus_mpie")
66 self
.mie
= Signal(name
="mstatus_mie")
67 self
.mprv
= Signal(name
="mstatus_mprv")
68 self
.tsr
= Signal(name
="mstatus_tsr")
69 self
.tw
= Signal(name
="mstatus_tw")
70 self
.tvm
= Signal(name
="mstatus_tvm")
71 self
.mxr
= Signal(name
="mstatus_mxr")
72 self
._sum
= Signal(name
="mstatus_sum")
73 self
.xs
= Signal(name
="mstatus_xs")
74 self
.fs
= Signal(name
="mstatus_fs")
75 self
.mpp
= Signal(2, name
="mstatus_mpp")
76 self
.spp
= Signal(name
="mstatus_spp")
77 self
.spie
= Signal(name
="mstatus_spie")
78 self
.upie
= Signal(name
="mstatus_upie")
79 self
.sie
= Signal(name
="mstatus_sie")
80 self
.uie
= Signal(name
="mstatus_uie")
83 if n
in ['make', 'mpp', 'comb', 'sync'] or n
.startswith("_"):
85 self
.comb
+= getattr(self
, n
).eq(0x0)
86 self
.comb
+= self
.mpp
.eq(0b11)
88 self
.sync
+= self
.mie
.eq(0)
89 self
.sync
+= self
.mpie
.eq(0)
93 self
.uie
, self
.sie
, Constant(0), self
.mie
,
94 self
.upie
, self
.spie
, Constant(0), self
.mpie
,
95 self
.spp
, Constant(0, 2), self
.mpp
,
96 self
.fs
, self
.xs
, self
.mprv
, self
._sum
,
97 self
.mxr
, self
.tvm
, self
.tw
, self
.tsr
,
99 (self
.xs
== Constant(0b11, 2)) |
(self
.fs
== Constant(0b11, 2))
104 def __init__(self
, comb
, sync
):
107 self
.meie
= Signal(name
="mie_meie")
108 self
.mtie
= Signal(name
="mie_mtie")
109 self
.msie
= Signal(name
="mie_msie")
110 self
.ueie
= Signal(name
="mie_ueie")
111 self
.stie
= Signal(name
="mie_stie")
112 self
.utie
= Signal(name
="mie_utie")
113 self
.ssie
= Signal(name
="mie_ssie")
114 self
.usie
= Signal(name
="mie_usie")
117 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
119 self
.comb
+= getattr(self
, n
).eq(0x0)
121 self
.sync
+= self
.meie
.eq(0)
122 self
.sync
+= self
.mtie
.eq(0)
123 self
.sync
+= self
.msie
.eq(0)
126 def __init__(self
, comb
, sync
):
129 self
.meip
= Signal(name
="mip_meip") # TODO: implement ext interrupts
130 self
.seip
= Signal(name
="mip_seip")
131 self
.ueip
= Signal(name
="mip_uiep")
132 self
.mtip
= Signal(name
="mip_mtip") # TODO: implement timer interrupts
133 self
.stip
= Signal(name
="mip_stip")
134 self
.msip
= Signal(name
="mip_stip")
135 self
.utip
= Signal(name
="mip_utip")
136 self
.ssip
= Signal(name
="mip_ssip")
137 self
.usip
= Signal(name
="mip_usip")
140 if n
in ['comb', 'sync'] or n
.startswith("_"):
142 self
.comb
+= getattr(self
, n
).eq(0x0)
146 def __init__(self
, comb
, sync
):
149 self
.mcause
= Signal(32)
150 self
.mepc
= Signal(32)
151 self
.mscratch
= Signal(32)
152 self
.sync
+= self
.mcause
.eq(0)
153 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
154 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
158 def __init__(self
, comb
, sync
):
161 self
.misa
= Signal(32)
163 for l
in list(string
.ascii_lowercase
):
164 value
= 1 if l
== 'i' else 0
165 cl
.append(Constant(value
))
166 cl
.append(Constant(0, 4))
167 cl
.append(Constant(0b01, 2))
168 self
.comb
+= self
.misa
.eq(Cat(cl
))
175 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
176 return Case(funct3
[:2],
177 { F3
.sb
: ls
.eq(Constant(0)),
178 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
179 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
180 "default": ls
.eq(Constant(1))
183 def get_lsbm(self
, dc
):
184 return Cat(Constant(1),
185 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
186 Constant(1), Constant(0)),
188 Constant(0b11, 2), Constant(0, 2)))
190 # XXX this happens to get done by various self.sync actions
191 #def reset_to_initial(self, m, mstatus, mie, registers):
192 # return [m.mcause.eq(0),
195 def write_register(self
, register_number
, value
):
196 return If(register_number
!= 0,
197 self
.registers
[register_number
].eq(value
)
200 def evaluate_csr_funct3_op(self
, funct3
, previous_value
, written_value
):
201 c
= { "default": Constant(0, 32)}
202 for f
in [F3
.csrrw
, F3
.csrrwi
]: c
[f
] = written_value
203 for f
in [F3
.csrrs
, F3
.csrrsi
]: c
[f
] = written_value | previous_value
204 for f
in [F3
.csrrc
, F3
.csrrci
]: c
[f
] = ~written_value
& previous_value
205 return Case(funct3
, c
)
208 self
.clk
= ClockSignal()
209 self
.reset
= ResetSignal()
210 self
.tty_write
= Signal()
211 self
.tty_write_data
= Signal(8)
212 self
.tty_write_busy
= Signal()
213 self
.switch_2
= Signal()
214 self
.switch_3
= Signal()
215 self
.led_1
= Signal()
216 self
.led_3
= Signal()
218 ram_size
= Constant(0x8000)
219 ram_start
= Constant(0x10000, 32)
220 reset_vector
= Signal(32)
223 reset_vector
.eq(ram_start
)
224 mtvec
.eq(ram_start
+ 0x40)
228 r
= Signal(32, name
="register%d" % i
)
230 self
.sync
+= r
.eq(Constant(0, 32))
231 self
.registers
= Array(l
)
233 mi
= MemoryInterface()
235 mii
= Instance("cpu_memory_interface", name
="memory_instance",
236 p_ram_size
= ram_size
,
237 p_ram_start
= ram_start
,
240 i_fetch_address
= mi
.fetch_address
,
241 o_fetch_data
= mi
.fetch_data
,
242 o_fetch_valid
= mi
.fetch_valid
,
243 i_rw_address
= mi
.rw_address
,
244 i_rw_byte_mask
= mi
.rw_byte_mask
,
245 i_rw_read_not_write
= mi
.rw_read_not_write
,
246 i_rw_active
= mi
.rw_active
,
247 i_rw_data_in
= mi
.rw_data_in
,
248 o_rw_data_out
= mi
.rw_data_out
,
249 o_rw_address_valid
= mi
.rw_address_valid
,
250 o_rw_wait
= mi
.rw_wait
,
251 o_tty_write
= self
.tty_write
,
252 o_tty_write_data
= self
.tty_write_data
,
253 i_tty_write_busy
= self
.tty_write_busy
,
254 i_switch_2
= self
.switch_2
,
255 i_switch_3
= self
.switch_3
,
256 o_led_1
= self
.led_1
,
261 fetch_act
= Signal(fetch_action
)
262 fetch_target_pc
= Signal(32)
263 fetch_output_pc
= Signal(32)
264 fetch_output_instruction
= Signal(32)
265 fetch_output_st
= Signal(fetch_output_state
)
267 fs
= Instance("CPUFetchStage", name
="fetch_stage",
270 o_memory_interface_fetch_address
= mi
.fetch_address
,
271 i_memory_interface_fetch_data
= mi
.fetch_data
,
272 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
273 i_fetch_action
= fetch_act
,
274 i_target_pc
= fetch_target_pc
,
275 o_output_pc
= fetch_output_pc
,
276 o_output_instruction
= fetch_output_instruction
,
277 o_output_state
= fetch_output_st
,
278 i_reset_vector
= reset_vector
,
285 cd
= Instance("CPUDecoder", name
="decoder",
286 i_instruction
= fetch_output_instruction
,
287 o_funct7
= dc
.funct7
,
288 o_funct3
= dc
.funct3
,
292 o_immediate
= dc
.immediate
,
293 o_opcode
= dc
.opcode
,
294 o_decode_action
= dc
.act
298 register_rs1
= Signal(32)
299 register_rs2
= Signal(32)
300 self
.comb
+= If(dc
.rs1
== 0,
303 register_rs1
.eq(self
.registers
[dc
.rs1
-1]))
304 self
.comb
+= If(dc
.rs2
== 0,
307 register_rs2
.eq(self
.registers
[dc
.rs2
-1]))
309 load_store_address
= Signal(32)
310 load_store_address_low_2
= Signal(2)
312 self
.comb
+= load_store_address
.eq(dc
.immediate
+ register_rs1
)
313 self
.comb
+= load_store_address_low_2
.eq(
314 dc
.immediate
[:2] + register_rs1
[:2])
316 load_store_misaligned
= Signal()
318 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
319 load_store_address_low_2
)
322 # XXX rwaddr not 31:2 any more
323 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
325 unshifted_load_store_byte_mask
= Signal(4)
327 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
329 # XXX yuck. this will cause migen simulation to fail
330 # (however conversion to verilog works)
331 self
.comb
+= mi
.rw_byte_mask
.eq(
332 _Operator("<<", [unshifted_load_store_byte_mask
,
333 load_store_address_low_2
]))
336 b3
= Mux(load_store_address_low_2
[1],
337 Mux(load_store_address_low_2
[0], register_rs2
[0:8],
339 Mux(load_store_address_low_2
[0], register_rs2
[16:24],
340 register_rs2
[24:32]))
341 b2
= Mux(load_store_address_low_2
[1], register_rs2
[0:8],
343 b1
= Mux(load_store_address_low_2
[0], register_rs2
[0:8],
345 b0
= register_rs2
[0:8]
347 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
350 unmasked_loaded_value
= Signal(32)
352 b0
= Mux(load_store_address_low_2
[1],
353 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
354 mi
.rw_data_out
[16:24]),
355 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
356 mi
.rw_data_out
[0:8]))
357 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
358 mi
.rw_data_out
[8:16])
359 b23
= mi
.rw_data_out
[16:32]
361 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
364 loaded_value
= Signal(32)
366 b0
= unmasked_loaded_value
[0:8]
367 b1
= Mux(dc
.funct3
[0:2] == 0,
368 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
369 unmasked_loaded_value
[8:16])
370 b2
= Mux(dc
.funct3
[1] == 0,
371 Replicate(~dc
.funct3
[2] &
372 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
373 unmasked_loaded_value
[7]),
375 unmasked_loaded_value
[16:32])
377 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
379 self
.comb
+= mi
.rw_active
.eq(~self
.reset
380 & (fetch_output_st
== fetch_output_state_valid
)
381 & ~load_store_misaligned
382 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
384 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
389 alu_result
= Signal(32)
391 self
.comb
+= alu_a
.eq(register_rs1
)
392 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
396 ali
= Instance("cpu_alu", name
="alu",
397 i_funct7
= dc
.funct7
,
398 i_funct3
= dc
.funct3
,
399 i_opcode
= dc
.opcode
,
402 o_result
= alu_result
406 lui_auipc_result
= Signal(32)
407 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
409 dc
.immediate
+ fetch_output_pc
))
411 self
.comb
+= fetch_target_pc
.eq(Cat(0,
412 Mux(dc
.opcode
!= OP
.jalr
,
413 fetch_output_pc
[1:32],
414 register_rs1
[1:32] + dc
.immediate
[1:32])))
416 misaligned_jump_target
= Signal()
417 self
.comb
+= misaligned_jump_target
.eq(fetch_target_pc
[1])
419 branch_arg_a
= Signal(32)
420 branch_arg_b
= Signal(32)
421 self
.comb
+= branch_arg_a
.eq(Cat( register_rs1
[0:31],
422 register_rs1
[31] ^ ~dc
.funct3
[1]))
423 self
.comb
+= branch_arg_b
.eq(Cat( register_rs2
[0:31],
424 register_rs2
[31] ^ ~dc
.funct3
[1]))
426 branch_taken
= Signal()
427 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
429 branch_arg_a
< branch_arg_b
,
430 branch_arg_a
== branch_arg_b
))
432 m
= M(self
.comb
, self
.sync
)
433 mstatus
= MStatus(self
.comb
, self
.sync
)
434 mie
= MIE(self
.comb
, self
.sync
)
436 misa
= Misa(self
.comb
, self
.sync
)
438 mvendorid
= Signal(32)
442 self
.comb
+= mvendorid
.eq(Constant(0, 32))
443 self
.comb
+= marchid
.eq(Constant(0, 32))
444 self
.comb
+= mimpid
.eq(Constant(0, 32))
445 self
.comb
+= mhartid
.eq(Constant(0, 32))
447 mip
= MIP(self
.comb
, self
.sync
)
449 csr_op_is_valid
= Signal()
451 if __name__
== "__main__":
453 print(verilog
.convert(example
,
456 example
.tty_write_data
,
457 example
.tty_write_busy
,
466 function `fetch_action get_fetch_action(
467 input `fetch_output_state fetch_output_state,
468 input `decode_action decode_action,
469 input load_store_misaligned,
470 input memory_interface_rw_address_valid,
471 input memory_interface_rw_wait,
473 input misaligned_jump_target,
474 input csr_op_is_valid
477 case(fetch_output_state)
478 `fetch_output_state_empty:
479 get_fetch_action = `fetch_action_default;
480 `fetch_output_state_trap:
481 get_fetch_action = `fetch_action_ack_trap;
482 `fetch_output_state_valid: begin
483 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
484 get_fetch_action = `fetch_action_error_trap;
486 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
487 get_fetch_action = `fetch_action_noerror_trap;
489 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
490 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
491 get_fetch_action = `fetch_action_error_trap;
493 else if(memory_interface_rw_wait) begin
494 get_fetch_action = `fetch_action_wait;
497 get_fetch_action = `fetch_action_default;
500 else if((decode_action & `decode_action_fence_i) != 0) begin
501 get_fetch_action = `fetch_action_fence;
503 else if((decode_action & `decode_action_branch) != 0) begin
504 if(branch_taken) begin
505 if(misaligned_jump_target) begin
506 get_fetch_action = `fetch_action_error_trap;
509 get_fetch_action = `fetch_action_jump;
514 get_fetch_action = `fetch_action_default;
517 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
518 if(misaligned_jump_target) begin
519 get_fetch_action = `fetch_action_error_trap;
522 get_fetch_action = `fetch_action_jump;
525 else if((decode_action & `decode_action_csr) != 0) begin
527 get_fetch_action = `fetch_action_default;
529 get_fetch_action = `fetch_action_error_trap;
532 get_fetch_action = `fetch_action_default;
536 get_fetch_action = 32'hXXXXXXXX;
541 assign fetch_action = get_fetch_action(
544 load_store_misaligned,
545 memory_interface_rw_address_valid,
546 memory_interface_rw_wait,
548 misaligned_jump_target,
554 mstatus_mpie = mstatus_mie;
556 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
557 if(fetch_action == `fetch_action_ack_trap) begin
558 mcause = `cause_instruction_access_fault;
560 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
561 mcause = `cause_illegal_instruction;
563 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
564 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
566 else if((decode_action & `decode_action_load) != 0) begin
567 if(load_store_misaligned)
568 mcause = `cause_load_address_misaligned;
570 mcause = `cause_load_access_fault;
572 else if((decode_action & `decode_action_store) != 0) begin
573 if(load_store_misaligned)
574 mcause = `cause_store_amo_address_misaligned;
576 mcause = `cause_store_amo_access_fault;
578 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
579 mcause = `cause_instruction_address_misaligned;
582 mcause = `cause_illegal_instruction;
587 wire [11:0] csr_number = decoder_immediate;
588 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
589 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
590 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
592 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
623 get_csr_op_is_valid = 0;
634 get_csr_op_is_valid = ~csr_writes;
643 get_csr_op_is_valid = 1;
650 // TODO: CSRs not implemented yet
651 get_csr_op_is_valid = 0;
656 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
658 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
659 wire [63:0] time_counter = 0; // TODO: implement time_counter
660 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
662 always @(posedge clk) begin:main_block
667 case(fetch_output_state)
668 `fetch_output_state_empty: begin
670 `fetch_output_state_trap: begin
673 `fetch_output_state_valid: begin:valid
674 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
677 else if((decode_action & `decode_action_load) != 0) begin
678 if(~memory_interface_rw_wait)
679 write_register(decoder_rd, loaded_value);
681 else if((decode_action & `decode_action_op_op_imm) != 0) begin
682 write_register(decoder_rd, alu_result);
684 else if((decode_action & `decode_action_lui_auipc) != 0) begin
685 write_register(decoder_rd, lui_auipc_result);
687 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
688 write_register(decoder_rd, fetch_output_pc + 4);
690 else if((decode_action & `decode_action_csr) != 0) begin:csr
691 reg [31:0] csr_output_value;
692 reg [31:0] csr_written_value;
693 csr_output_value = 32'hXXXXXXXX;
694 csr_written_value = 32'hXXXXXXXX;
697 csr_output_value = cycle_counter[31:0];
700 csr_output_value = time_counter[31:0];
703 csr_output_value = instret_counter[31:0];
706 csr_output_value = cycle_counter[63:32];
709 csr_output_value = time_counter[63:32];
712 csr_output_value = instret_counter[63:32];
714 `csr_mvendorid: begin
715 csr_output_value = mvendorid;
718 csr_output_value = marchid;
721 csr_output_value = mimpid;
724 csr_output_value = mhartid;
727 csr_output_value = misa;
730 csr_output_value = make_mstatus(mstatus_tsr,
746 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
748 mstatus_mpie = csr_written_value[7];
749 mstatus_mie = csr_written_value[3];
753 csr_output_value = 0;
754 csr_output_value[11] = mie_meie;
755 csr_output_value[9] = mie_seie;
756 csr_output_value[8] = mie_ueie;
757 csr_output_value[7] = mie_mtie;
758 csr_output_value[5] = mie_stie;
759 csr_output_value[4] = mie_utie;
760 csr_output_value[3] = mie_msie;
761 csr_output_value[1] = mie_ssie;
762 csr_output_value[0] = mie_usie;
763 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
765 mie_meie = csr_written_value[11];
766 mie_mtie = csr_written_value[7];
767 mie_msie = csr_written_value[3];
771 csr_output_value = mtvec;
774 csr_output_value = mscratch;
775 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
777 mscratch = csr_written_value;
780 csr_output_value = mepc;
781 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
783 mepc = csr_written_value;
786 csr_output_value = mcause;
787 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
789 mcause = csr_written_value;
792 csr_output_value = 0;
793 csr_output_value[11] = mip_meip;
794 csr_output_value[9] = mip_seip;
795 csr_output_value[8] = mip_ueip;
796 csr_output_value[7] = mip_mtip;
797 csr_output_value[5] = mip_stip;
798 csr_output_value[4] = mip_utip;
799 csr_output_value[3] = mip_msip;
800 csr_output_value[1] = mip_ssip;
801 csr_output_value[0] = mip_usip;
805 write_register(decoder_rd, csr_output_value);
807 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin