3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 from migen
.fhdl
import verilog
32 from riscvdefs
import *
40 #self.clk = ClockSignal()
41 #self.reset = ResetSignal()
42 self
.tty_write
= Signal()
43 self
.tty_write_data
= Signal(8)
44 self
.tty_write_busy
= Signal()
45 self
.switch_2
= Signal()
46 self
.switch_3
= Signal()
50 ram_size
= Constant(0x8000)
51 ram_start
= Constant(0x10000, 32)
52 reset_vector
= Signal(32)
55 reset_vector
.eq(ram_start
)
56 mtvec
.eq(ram_start
+ 0x40)
60 l
.append(Signal(32, name
="register%d" % i
))
63 #self.sync += self.registers[0].eq(0)
64 #self.sync += self.registers[1].eq(0)
66 memory_interface_fetch_address
= Signal(32) # XXX [2:]
67 memory_interface_fetch_data
= Signal(32)
68 memory_interface_fetch_valid
= Signal()
69 memory_interface_rw_address
= Signal(32) # XXX [2:]
70 memory_interface_rw_byte_mask
= Signal(4)
71 memory_interface_rw_read_not_write
= Signal()
72 memory_interface_rw_active
= Signal()
73 memory_interface_rw_data_in
= Signal(32)
74 memory_interface_rw_data_out
= Signal(32)
75 memory_interface_rw_address_valid
= Signal()
76 memory_interface_rw_wait
= Signal()
78 mi
= Instance("cpu_memory_interface", name
="memory_instance",
79 p_ram_size
= ram_size
,
80 p_ram_start
= ram_start
,
83 i_fetch_address
= memory_interface_fetch_address
,
84 o_fetch_data
= memory_interface_fetch_data
,
85 o_fetch_valid
= memory_interface_fetch_valid
,
86 i_rw_address
= memory_interface_rw_address
,
87 i_rw_byte_mask
= memory_interface_rw_byte_mask
,
88 i_rw_read_not_write
= memory_interface_rw_read_not_write
,
89 i_rw_active
= memory_interface_rw_active
,
90 i_rw_data_in
= memory_interface_rw_data_in
,
91 o_rw_data_out
= memory_interface_rw_data_out
,
92 o_rw_address_valid
= memory_interface_rw_address_valid
,
93 o_rw_wait
= memory_interface_rw_wait
,
94 o_tty_write
= self
.tty_write
,
95 o_tty_write_data
= self
.tty_write_data
,
96 i_tty_write_busy
= self
.tty_write_busy
,
97 i_switch_2
= self
.switch_2
,
98 i_switch_3
= self
.switch_3
,
104 fetch_act
= Signal(fetch_action
)
105 fetch_target_pc
= Signal(32)
106 fetch_output_pc
= Signal(32)
107 fetch_output_instruction
= Signal(32)
108 fetch_output_st
= Signal(fetch_output_state
)
110 fs
= Instance("CPUFetchStage", name
="fetch_stage",
113 o_memory_interface_fetch_address
= memory_interface_fetch_address
,
114 i_memory_interface_fetch_data
= memory_interface_fetch_data
,
115 i_memory_interface_fetch_valid
= memory_interface_fetch_valid
,
116 i_fetch_action
= fetch_act
,
117 i_target_pc
= fetch_target_pc
,
118 o_output_pc
= fetch_output_pc
,
119 o_output_instruction
= fetch_output_instruction
,
120 o_output_state
= fetch_output_st
,
121 i_reset_vector
= reset_vector
,
126 decoder_funct7
= Signal(7)
127 decoder_funct3
= Signal(3)
128 decoder_rd
= Signal(5)
129 decoder_rs1
= Signal(5)
130 decoder_rs2
= Signal(5)
131 decoder_immediate
= Signal(32)
132 decoder_opcode
= Signal(7)
133 decode_act
= Signal(decode_action
)
135 cd
= Instance("CPUDecoder", name
="decoder",
136 i_instruction
= fetch_output_instruction
,
137 o_funct7
= decoder_funct7
,
138 o_funct3
= decoder_funct3
,
142 o_immediate
= decoder_immediate
,
143 o_opcode
= decoder_opcode
,
144 o_decode_action
= decode_act
148 register_rs1
= Signal(32)
149 register_rs2
= Signal(32)
150 self
.comb
+= If(decoder_rs1
== 0,
153 register_rs1
.eq(registers
[decoder_rs1
-1]))
154 self
.comb
+= If(decoder_rs2
== 0,
157 register_rs2
.eq(registers
[decoder_rs2
-1]))
159 load_store_address
= Signal(32)
160 load_store_address_low_2
= Signal(2)
162 self
.comb
+= load_store_address
.eq(decoder_immediate
+ register_rs1
)
163 self
.comb
+= load_store_address_low_2
.eq(
164 decoder_immediate
[:2] + register_rs1
[:2])
166 load_store_misaligned
= Signal()
168 lsa
= self
.get_ls_misaligned(load_store_misaligned
, decoder_funct3
,
169 load_store_address_low_2
)
172 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
173 return Case(funct3
[:2],
174 { F3
.sb
: ls
.eq(Constant(0)),
175 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
176 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
177 "default": ls
.eq(Constant(1))
181 if __name__
== "__main__":
183 print(verilog
.convert(example
,
186 example
.tty_write_data
,
187 example
.tty_write_busy
,
196 function get_load_store_misaligned(
198 input [1:0] load_store_address_low_2
203 get_load_store_misaligned = 0;
205 get_load_store_misaligned = load_store_address_low_2[0] != 0;
207 get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
209 get_load_store_misaligned = 1'bX;
214 wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
216 assign memory_interface_rw_address = load_store_address[31:2];
218 wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
220 assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
222 assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
223 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
224 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
225 assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
226 assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
227 assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
229 wire [31:0] unmasked_loaded_value;
231 assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
232 ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
233 : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
234 assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
235 assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
237 wire [31:0] loaded_value;
239 assign loaded_value[7:0] = unmasked_loaded_value[7:0];
240 assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
241 assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
243 assign memory_interface_rw_active = ~reset
244 & (fetch_output_state == `fetch_output_state_valid)
245 & ~load_store_misaligned
246 & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
248 assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
250 wire [31:0] alu_a = register_rs1;
251 wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
252 wire [31:0] alu_result;
255 .funct7(decoder_funct7),
256 .funct3(decoder_funct3),
257 .opcode(decoder_opcode),
263 wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
265 assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
266 assign fetch_target_pc[0] = 0;
268 wire misaligned_jump_target = fetch_target_pc[1];
270 wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
271 wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
273 wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
275 reg [31:0] mcause = 0;
276 reg [31:0] mepc = 32'hXXXXXXXX;
277 reg [31:0] mscratch = 32'hXXXXXXXX;
279 reg mstatus_mpie = 1'bX;
281 parameter mstatus_mprv = 0;
282 parameter mstatus_tsr = 0;
283 parameter mstatus_tw = 0;
284 parameter mstatus_tvm = 0;
285 parameter mstatus_mxr = 0;
286 parameter mstatus_sum = 0;
287 parameter mstatus_xs = 0;
288 parameter mstatus_fs = 0;
289 parameter mstatus_mpp = 2'b11;
290 parameter mstatus_spp = 0;
291 parameter mstatus_spie = 0;
292 parameter mstatus_upie = 0;
293 parameter mstatus_sie = 0;
294 parameter mstatus_uie = 0;
299 parameter mie_seie = 0;
300 parameter mie_ueie = 0;
301 parameter mie_stie = 0;
302 parameter mie_utie = 0;
303 parameter mie_ssie = 0;
304 parameter mie_usie = 0;
306 task reset_to_initial;
310 mscratch = 32'hXXXXXXXX;
316 registers['h01] <= 32'hXXXXXXXX;
317 registers['h02] <= 32'hXXXXXXXX;
318 registers['h03] <= 32'hXXXXXXXX;
319 registers['h04] <= 32'hXXXXXXXX;
320 registers['h05] <= 32'hXXXXXXXX;
321 registers['h06] <= 32'hXXXXXXXX;
322 registers['h07] <= 32'hXXXXXXXX;
323 registers['h08] <= 32'hXXXXXXXX;
324 registers['h09] <= 32'hXXXXXXXX;
325 registers['h0A] <= 32'hXXXXXXXX;
326 registers['h0B] <= 32'hXXXXXXXX;
327 registers['h0C] <= 32'hXXXXXXXX;
328 registers['h0D] <= 32'hXXXXXXXX;
329 registers['h0E] <= 32'hXXXXXXXX;
330 registers['h0F] <= 32'hXXXXXXXX;
331 registers['h10] <= 32'hXXXXXXXX;
332 registers['h11] <= 32'hXXXXXXXX;
333 registers['h12] <= 32'hXXXXXXXX;
334 registers['h13] <= 32'hXXXXXXXX;
335 registers['h14] <= 32'hXXXXXXXX;
336 registers['h15] <= 32'hXXXXXXXX;
337 registers['h16] <= 32'hXXXXXXXX;
338 registers['h17] <= 32'hXXXXXXXX;
339 registers['h18] <= 32'hXXXXXXXX;
340 registers['h19] <= 32'hXXXXXXXX;
341 registers['h1A] <= 32'hXXXXXXXX;
342 registers['h1B] <= 32'hXXXXXXXX;
343 registers['h1C] <= 32'hXXXXXXXX;
344 registers['h1D] <= 32'hXXXXXXXX;
345 registers['h1E] <= 32'hXXXXXXXX;
346 registers['h1F] <= 32'hXXXXXXXX;
350 task write_register(input [4:0] register_number, input [31:0] value);
352 if(register_number != 0)
353 registers[register_number] <= value;
357 function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
360 `funct3_csrrw, `funct3_csrrwi:
361 evaluate_csr_funct3_operation = written_value;
362 `funct3_csrrs, `funct3_csrrsi:
363 evaluate_csr_funct3_operation = written_value | previous_value;
364 `funct3_csrrc, `funct3_csrrci:
365 evaluate_csr_funct3_operation = ~written_value & previous_value;
367 evaluate_csr_funct3_operation = 32'hXXXXXXXX;
372 parameter misa_a = 1'b0;
373 parameter misa_b = 1'b0;
374 parameter misa_c = 1'b0;
375 parameter misa_d = 1'b0;
376 parameter misa_e = 1'b0;
377 parameter misa_f = 1'b0;
378 parameter misa_g = 1'b0;
379 parameter misa_h = 1'b0;
380 parameter misa_i = 1'b1;
381 parameter misa_j = 1'b0;
382 parameter misa_k = 1'b0;
383 parameter misa_l = 1'b0;
384 parameter misa_m = 1'b0;
385 parameter misa_n = 1'b0;
386 parameter misa_o = 1'b0;
387 parameter misa_p = 1'b0;
388 parameter misa_q = 1'b0;
389 parameter misa_r = 1'b0;
390 parameter misa_s = 1'b0;
391 parameter misa_t = 1'b0;
392 parameter misa_u = 1'b0;
393 parameter misa_v = 1'b0;
394 parameter misa_w = 1'b0;
395 parameter misa_x = 1'b0;
396 parameter misa_y = 1'b0;
397 parameter misa_z = 1'b0;
428 parameter mvendorid = 32'b0;
429 parameter marchid = 32'b0;
430 parameter mimpid = 32'b0;
431 parameter mhartid = 32'b0;
433 function [31:0] make_mstatus(input mstatus_tsr,
439 input [1:0] mstatus_xs,
440 input [1:0] mstatus_fs,
441 input [1:0] mstatus_mpp,
450 make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
474 wire mip_meip = 0; // TODO: implement external interrupts
475 parameter mip_seip = 0;
476 parameter mip_ueip = 0;
477 wire mip_mtip = 0; // TODO: implement timer interrupts
478 parameter mip_stip = 0;
479 parameter mip_utip = 0;
480 parameter mip_msip = 0;
481 parameter mip_ssip = 0;
482 parameter mip_usip = 0;
484 wire csr_op_is_valid;
486 function `fetch_action get_fetch_action(
487 input `fetch_output_state fetch_output_state,
488 input `decode_action decode_action,
489 input load_store_misaligned,
490 input memory_interface_rw_address_valid,
491 input memory_interface_rw_wait,
493 input misaligned_jump_target,
494 input csr_op_is_valid
497 case(fetch_output_state)
498 `fetch_output_state_empty:
499 get_fetch_action = `fetch_action_default;
500 `fetch_output_state_trap:
501 get_fetch_action = `fetch_action_ack_trap;
502 `fetch_output_state_valid: begin
503 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
504 get_fetch_action = `fetch_action_error_trap;
506 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
507 get_fetch_action = `fetch_action_noerror_trap;
509 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
510 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
511 get_fetch_action = `fetch_action_error_trap;
513 else if(memory_interface_rw_wait) begin
514 get_fetch_action = `fetch_action_wait;
517 get_fetch_action = `fetch_action_default;
520 else if((decode_action & `decode_action_fence_i) != 0) begin
521 get_fetch_action = `fetch_action_fence;
523 else if((decode_action & `decode_action_branch) != 0) begin
524 if(branch_taken) begin
525 if(misaligned_jump_target) begin
526 get_fetch_action = `fetch_action_error_trap;
529 get_fetch_action = `fetch_action_jump;
534 get_fetch_action = `fetch_action_default;
537 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
538 if(misaligned_jump_target) begin
539 get_fetch_action = `fetch_action_error_trap;
542 get_fetch_action = `fetch_action_jump;
545 else if((decode_action & `decode_action_csr) != 0) begin
547 get_fetch_action = `fetch_action_default;
549 get_fetch_action = `fetch_action_error_trap;
552 get_fetch_action = `fetch_action_default;
556 get_fetch_action = 32'hXXXXXXXX;
561 assign fetch_action = get_fetch_action(
564 load_store_misaligned,
565 memory_interface_rw_address_valid,
566 memory_interface_rw_wait,
568 misaligned_jump_target,
574 mstatus_mpie = mstatus_mie;
576 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
577 if(fetch_action == `fetch_action_ack_trap) begin
578 mcause = `cause_instruction_access_fault;
580 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
581 mcause = `cause_illegal_instruction;
583 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
584 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
586 else if((decode_action & `decode_action_load) != 0) begin
587 if(load_store_misaligned)
588 mcause = `cause_load_address_misaligned;
590 mcause = `cause_load_access_fault;
592 else if((decode_action & `decode_action_store) != 0) begin
593 if(load_store_misaligned)
594 mcause = `cause_store_amo_address_misaligned;
596 mcause = `cause_store_amo_access_fault;
598 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
599 mcause = `cause_instruction_address_misaligned;
602 mcause = `cause_illegal_instruction;
607 wire [11:0] csr_number = decoder_immediate;
608 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
609 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
610 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
612 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
643 get_csr_op_is_valid = 0;
654 get_csr_op_is_valid = ~csr_writes;
663 get_csr_op_is_valid = 1;
670 // TODO: CSRs not implemented yet
671 get_csr_op_is_valid = 0;
676 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
678 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
679 wire [63:0] time_counter = 0; // TODO: implement time_counter
680 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
682 always @(posedge clk) begin:main_block
687 case(fetch_output_state)
688 `fetch_output_state_empty: begin
690 `fetch_output_state_trap: begin
693 `fetch_output_state_valid: begin:valid
694 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
697 else if((decode_action & `decode_action_load) != 0) begin
698 if(~memory_interface_rw_wait)
699 write_register(decoder_rd, loaded_value);
701 else if((decode_action & `decode_action_op_op_imm) != 0) begin
702 write_register(decoder_rd, alu_result);
704 else if((decode_action & `decode_action_lui_auipc) != 0) begin
705 write_register(decoder_rd, lui_auipc_result);
707 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
708 write_register(decoder_rd, fetch_output_pc + 4);
710 else if((decode_action & `decode_action_csr) != 0) begin:csr
711 reg [31:0] csr_output_value;
712 reg [31:0] csr_written_value;
713 csr_output_value = 32'hXXXXXXXX;
714 csr_written_value = 32'hXXXXXXXX;
717 csr_output_value = cycle_counter[31:0];
720 csr_output_value = time_counter[31:0];
723 csr_output_value = instret_counter[31:0];
726 csr_output_value = cycle_counter[63:32];
729 csr_output_value = time_counter[63:32];
732 csr_output_value = instret_counter[63:32];
734 `csr_mvendorid: begin
735 csr_output_value = mvendorid;
738 csr_output_value = marchid;
741 csr_output_value = mimpid;
744 csr_output_value = mhartid;
747 csr_output_value = misa;
750 csr_output_value = make_mstatus(mstatus_tsr,
766 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
768 mstatus_mpie = csr_written_value[7];
769 mstatus_mie = csr_written_value[3];
773 csr_output_value = 0;
774 csr_output_value[11] = mie_meie;
775 csr_output_value[9] = mie_seie;
776 csr_output_value[8] = mie_ueie;
777 csr_output_value[7] = mie_mtie;
778 csr_output_value[5] = mie_stie;
779 csr_output_value[4] = mie_utie;
780 csr_output_value[3] = mie_msie;
781 csr_output_value[1] = mie_ssie;
782 csr_output_value[0] = mie_usie;
783 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
785 mie_meie = csr_written_value[11];
786 mie_mtie = csr_written_value[7];
787 mie_msie = csr_written_value[3];
791 csr_output_value = mtvec;
794 csr_output_value = mscratch;
795 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
797 mscratch = csr_written_value;
800 csr_output_value = mepc;
801 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
803 mepc = csr_written_value;
806 csr_output_value = mcause;
807 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
809 mcause = csr_written_value;
812 csr_output_value = 0;
813 csr_output_value[11] = mip_meip;
814 csr_output_value[9] = mip_seip;
815 csr_output_value[8] = mip_ueip;
816 csr_output_value[7] = mip_mtip;
817 csr_output_value[5] = mip_stip;
818 csr_output_value[4] = mip_utip;
819 csr_output_value[3] = mip_msip;
820 csr_output_value[1] = mip_ssip;
821 csr_output_value[0] = mip_usip;
825 write_register(decoder_rd, csr_output_value);
827 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin