3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
62 def __init__(self
, comb
, sync
):
65 self
.mpie
= Signal(name
="mstatus_mpie")
66 self
.mie
= Signal(name
="mstatus_mie")
67 self
.mprv
= Signal(name
="mstatus_mprv")
68 self
.tsr
= Signal(name
="mstatus_tsr")
69 self
.tw
= Signal(name
="mstatus_tw")
70 self
.tvm
= Signal(name
="mstatus_tvm")
71 self
.mxr
= Signal(name
="mstatus_mxr")
72 self
._sum
= Signal(name
="mstatus_sum")
73 self
.xs
= Signal(name
="mstatus_xs")
74 self
.fs
= Signal(name
="mstatus_fs")
75 self
.mpp
= Signal(2, name
="mstatus_mpp")
76 self
.spp
= Signal(name
="mstatus_spp")
77 self
.spie
= Signal(name
="mstatus_spie")
78 self
.upie
= Signal(name
="mstatus_upie")
79 self
.sie
= Signal(name
="mstatus_sie")
80 self
.uie
= Signal(name
="mstatus_uie")
83 if n
in ['make', 'mpp', 'comb', 'sync'] or n
.startswith("_"):
85 self
.comb
+= getattr(self
, n
).eq(0x0)
86 self
.comb
+= self
.mpp
.eq(0b11)
88 self
.sync
+= self
.mie
.eq(0)
89 self
.sync
+= self
.mpie
.eq(0)
93 self
.uie
, self
.sie
, Constant(0), self
.mie
,
94 self
.upie
, self
.spie
, Constant(0), self
.mpie
,
95 self
.spp
, Constant(0, 2), self
.mpp
,
96 self
.fs
, self
.xs
, self
.mprv
, self
._sum
,
97 self
.mxr
, self
.tvm
, self
.tw
, self
.tsr
,
99 (self
.xs
== Constant(0b11, 2)) |
(self
.fs
== Constant(0b11, 2))
104 def __init__(self
, comb
, sync
):
107 self
.meie
= Signal(name
="mie_meie")
108 self
.mtie
= Signal(name
="mie_mtie")
109 self
.msie
= Signal(name
="mie_msie")
110 self
.ueie
= Signal(name
="mie_ueie")
111 self
.stie
= Signal(name
="mie_stie")
112 self
.utie
= Signal(name
="mie_utie")
113 self
.ssie
= Signal(name
="mie_ssie")
114 self
.usie
= Signal(name
="mie_usie")
117 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
119 self
.comb
+= getattr(self
, n
).eq(0x0)
121 self
.sync
+= self
.meie
.eq(0)
122 self
.sync
+= self
.mtie
.eq(0)
123 self
.sync
+= self
.msie
.eq(0)
126 def __init__(self
, comb
, sync
):
129 self
.meip
= Signal(name
="mip_meip") # TODO: implement ext interrupts
130 self
.seip
= Signal(name
="mip_seip")
131 self
.ueip
= Signal(name
="mip_uiep")
132 self
.mtip
= Signal(name
="mip_mtip") # TODO: implement timer interrupts
133 self
.stip
= Signal(name
="mip_stip")
134 self
.msip
= Signal(name
="mip_stip")
135 self
.utip
= Signal(name
="mip_utip")
136 self
.ssip
= Signal(name
="mip_ssip")
137 self
.usip
= Signal(name
="mip_usip")
140 if n
in ['comb', 'sync'] or n
.startswith("_"):
142 self
.comb
+= getattr(self
, n
).eq(0x0)
146 def __init__(self
, comb
, sync
):
149 self
.mcause
= Signal(32)
150 self
.mepc
= Signal(32)
151 self
.mscratch
= Signal(32)
152 self
.sync
+= self
.mcause
.eq(0)
153 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
154 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
158 def __init__(self
, comb
, sync
):
161 self
.misa
= Signal(32)
163 for l
in list(string
.ascii_lowercase
):
164 value
= 1 if l
== 'i' else 0
165 cl
.append(Constant(value
))
166 cl
.append(Constant(0, 4))
167 cl
.append(Constant(0b01, 2))
168 self
.comb
+= self
.misa
.eq(Cat(cl
))
172 def __init__(self
, comb
, sync
):
175 self
.action
= Signal(fetch_action
, name
="fetch_action")
176 self
.target_pc
= Signal(32, name
="fetch_target_pc")
177 self
.output_pc
= Signal(32, name
="fetch_output_pc")
178 self
.output_instruction
= Signal(32, name
="fetch_ouutput_instruction")
179 self
.output_state
= Signal(fetch_output_state
,name
="fetch_output_state")
181 def get_fetch_action(self
, dc
, load_store_misaligned
, mi
,
182 branch_taken
, misaligned_jump_target
,
185 c
["default"] = self
.action
.eq(FA
.default
) # XXX should be 32'XXXXXXXX?
186 c
[FOS
.empty
] = self
.action
.eq(FA
.default
)
187 c
[FOS
.trap
] = self
.action
.eq(FA
.ack_trap
)
189 # illegal instruction -> error trap
190 i
= If((dc
.act
& DA
.trap_illegal_instruction
) != 0,
191 self
.action
.eq(FA
.error_trap
)
194 # ecall / ebreak -> noerror trap
195 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
196 self
.action
.eq(FA
.noerror_trap
))
198 # load/store: check alignment, check wait
199 i
= i
.Elif((dc
.act
& (DA
.load | DA
.store
)) != 0,
200 If((load_store_misaligned | ~mi
.rw_address_valid
),
201 self
.action
.eq(FA
.error_trap
) # misaligned or invalid addr
203 self
.action
.eq(FA
.wait
) # wait
205 self
.action
.eq(FA
.default
) # ok
210 i
= i
.Elif((dc
.act
& DA
.fence
) != 0,
211 self
.action
.eq(FA
.fence
))
213 # branch -> misaligned=error, otherwise jump
214 i
= i
.Elif((dc
.act
& DA
.branch
) != 0,
215 If(misaligned_jump_target
,
216 self
.action
.eq(FA
.error_trap
)
218 self
.action
.eq(FA
.jump
)
222 # jal/jalr -> misaligned=error, otherwise jump
223 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
224 If(misaligned_jump_target
,
225 self
.action
.eq(FA
.error_trap
)
227 self
.action
.eq(FA
.jump
)
231 # csr -> opvalid=ok, else error trap
232 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
234 self
.action
.eq(FA
.default
)
236 self
.action
.eq(FA
.error_trap
)
242 return Case(self
.output_state
, c
)
249 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
250 """ returns whether a load/store is misaligned
252 return Case(funct3
[:2],
253 { F3
.sb
: ls
.eq(Constant(0)),
254 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
255 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
256 "default": ls
.eq(Constant(1))
259 def get_lsbm(self
, dc
):
260 return Cat(Constant(1),
261 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
262 Constant(1), Constant(0)),
264 Constant(0b11, 2), Constant(0, 2)))
266 # XXX this happens to get done by various self.sync actions
267 #def reset_to_initial(self, m, mstatus, mie, registers):
268 # return [m.mcause.eq(0),
271 def write_register(self
, register_number
, value
):
272 return If(register_number
!= 0,
273 self
.registers
[register_number
].eq(value
)
276 def evaluate_csr_funct3_op(self
, funct3
, previous_value
, written_value
):
277 c
= { "default": Constant(0, 32)}
278 for f
in [F3
.csrrw
, F3
.csrrwi
]: c
[f
] = written_value
279 for f
in [F3
.csrrs
, F3
.csrrsi
]: c
[f
] = written_value | previous_value
280 for f
in [F3
.csrrc
, F3
.csrrci
]: c
[f
] = ~written_value
& previous_value
281 return Case(funct3
, c
)
283 def handle_trap(self
, m
, ms
, ft
, dc
, load_store_misaligned
):
284 s
= [ms
.mpie
.eq(ms
.mie
),
286 m
.mepc
.eq(Mux(ft
.action
== FA
.noerror_trap
,
290 # fetch action ack trap
291 i
= If(ft
.action
== FA
.ack_trap
,
292 m
.mcause
.eq(cause_instruction_access_fault
)
296 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
297 m
.mcause
.eq(Mux(dc
.immediate
[0],
298 cause_machine_environment_call
,
303 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
304 If(load_store_misaligned
,
305 m
.mcause
.eq(cause_load_address_misaligned
)
307 m
.mcause
.eq(cause_load_access_fault
)
312 i
= i
.Elif((dc
.act
& DA
.store
) != 0,
313 If(load_store_misaligned
,
314 m
.mcause
.eq(cause_store_amo_address_misaligned
)
316 m
.mcause
.eq(cause_store_amo_access_fault
)
320 # jal/jalr -> misaligned=error, otherwise jump
321 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr | DA
.branch
)) != 0,
322 m
.mcause
.eq(cause_instruction_address_misaligned
)
325 # defaults to illegal instruction
326 i
= i
.Else(m
.mcause
.eq(cause_illegal_instruction
))
334 mstatus_mpie = mstatus_mie;
336 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
337 if(fetch_action == `fetch_action_ack_trap) begin
338 mcause = `cause_instruction_access_fault;
340 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
341 mcause = `cause_illegal_instruction;
343 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
344 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
346 else if((decode_action & `decode_action_load) != 0) begin
347 if(load_store_misaligned)
348 mcause = `cause_load_address_misaligned;
350 mcause = `cause_load_access_fault;
352 else if((decode_action & `decode_action_store) != 0) begin
353 if(load_store_misaligned)
354 mcause = `cause_store_amo_address_misaligned;
356 mcause = `cause_store_amo_access_fault;
358 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
359 mcause = `cause_instruction_address_misaligned;
362 mcause = `cause_illegal_instruction;
369 self
.clk
= ClockSignal()
370 self
.reset
= ResetSignal()
371 self
.tty_write
= Signal()
372 self
.tty_write_data
= Signal(8)
373 self
.tty_write_busy
= Signal()
374 self
.switch_2
= Signal()
375 self
.switch_3
= Signal()
376 self
.led_1
= Signal()
377 self
.led_3
= Signal()
379 ram_size
= Constant(0x8000)
380 ram_start
= Constant(0x10000, 32)
381 reset_vector
= Signal(32)
384 reset_vector
.eq(ram_start
)
385 mtvec
.eq(ram_start
+ 0x40)
389 r
= Signal(32, name
="register%d" % i
)
391 self
.sync
+= r
.eq(Constant(0, 32))
392 self
.registers
= Array(l
)
394 mi
= MemoryInterface()
396 mii
= Instance("cpu_memory_interface", name
="memory_instance",
397 p_ram_size
= ram_size
,
398 p_ram_start
= ram_start
,
401 i_fetch_address
= mi
.fetch_address
,
402 o_fetch_data
= mi
.fetch_data
,
403 o_fetch_valid
= mi
.fetch_valid
,
404 i_rw_address
= mi
.rw_address
,
405 i_rw_byte_mask
= mi
.rw_byte_mask
,
406 i_rw_read_not_write
= mi
.rw_read_not_write
,
407 i_rw_active
= mi
.rw_active
,
408 i_rw_data_in
= mi
.rw_data_in
,
409 o_rw_data_out
= mi
.rw_data_out
,
410 o_rw_address_valid
= mi
.rw_address_valid
,
411 o_rw_wait
= mi
.rw_wait
,
412 o_tty_write
= self
.tty_write
,
413 o_tty_write_data
= self
.tty_write_data
,
414 i_tty_write_busy
= self
.tty_write_busy
,
415 i_switch_2
= self
.switch_2
,
416 i_switch_3
= self
.switch_3
,
417 o_led_1
= self
.led_1
,
422 ft
= Fetch(self
.comb
, self
.sync
)
424 fs
= Instance("CPUFetchStage", name
="fetch_stage",
427 o_memory_interface_fetch_address
= mi
.fetch_address
,
428 i_memory_interface_fetch_data
= mi
.fetch_data
,
429 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
430 i_fetch_action
= ft
.action
,
431 i_target_pc
= ft
.target_pc
,
432 o_output_pc
= ft
.output_pc
,
433 o_output_instruction
= ft
.output_instruction
,
434 o_output_state
= ft
.output_state
,
435 i_reset_vector
= reset_vector
,
442 cd
= Instance("CPUDecoder", name
="decoder",
443 i_instruction
= ft
.output_instruction
,
444 o_funct7
= dc
.funct7
,
445 o_funct3
= dc
.funct3
,
449 o_immediate
= dc
.immediate
,
450 o_opcode
= dc
.opcode
,
451 o_decode_action
= dc
.act
455 register_rs1
= Signal(32)
456 register_rs2
= Signal(32)
457 self
.comb
+= If(dc
.rs1
== 0,
460 register_rs1
.eq(self
.registers
[dc
.rs1
-1]))
461 self
.comb
+= If(dc
.rs2
== 0,
464 register_rs2
.eq(self
.registers
[dc
.rs2
-1]))
466 load_store_address
= Signal(32)
467 load_store_address_low_2
= Signal(2)
469 self
.comb
+= load_store_address
.eq(dc
.immediate
+ register_rs1
)
470 self
.comb
+= load_store_address_low_2
.eq(
471 dc
.immediate
[:2] + register_rs1
[:2])
473 load_store_misaligned
= Signal()
475 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
476 load_store_address_low_2
)
479 # XXX rwaddr not 31:2 any more
480 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
482 unshifted_load_store_byte_mask
= Signal(4)
484 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
486 # XXX yuck. this will cause migen simulation to fail
487 # (however conversion to verilog works)
488 self
.comb
+= mi
.rw_byte_mask
.eq(
489 _Operator("<<", [unshifted_load_store_byte_mask
,
490 load_store_address_low_2
]))
493 b3
= Mux(load_store_address_low_2
[1],
494 Mux(load_store_address_low_2
[0], register_rs2
[0:8],
496 Mux(load_store_address_low_2
[0], register_rs2
[16:24],
497 register_rs2
[24:32]))
498 b2
= Mux(load_store_address_low_2
[1], register_rs2
[0:8],
500 b1
= Mux(load_store_address_low_2
[0], register_rs2
[0:8],
502 b0
= register_rs2
[0:8]
504 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
507 unmasked_loaded_value
= Signal(32)
509 b0
= Mux(load_store_address_low_2
[1],
510 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
511 mi
.rw_data_out
[16:24]),
512 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
513 mi
.rw_data_out
[0:8]))
514 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
515 mi
.rw_data_out
[8:16])
516 b23
= mi
.rw_data_out
[16:32]
518 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
521 loaded_value
= Signal(32)
523 b0
= unmasked_loaded_value
[0:8]
524 b1
= Mux(dc
.funct3
[0:2] == 0,
525 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
526 unmasked_loaded_value
[8:16])
527 b2
= Mux(dc
.funct3
[1] == 0,
528 Replicate(~dc
.funct3
[2] &
529 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
530 unmasked_loaded_value
[7]),
532 unmasked_loaded_value
[16:32])
534 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
536 self
.comb
+= mi
.rw_active
.eq(~self
.reset
537 & (ft
.output_state
== FOS
.valid
)
538 & ~load_store_misaligned
539 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
541 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
546 alu_result
= Signal(32)
548 self
.comb
+= alu_a
.eq(register_rs1
)
549 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
553 ali
= Instance("cpu_alu", name
="alu",
554 i_funct7
= dc
.funct7
,
555 i_funct3
= dc
.funct3
,
556 i_opcode
= dc
.opcode
,
559 o_result
= alu_result
563 lui_auipc_result
= Signal(32)
564 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
566 dc
.immediate
+ ft
.output_pc
))
568 self
.comb
+= ft
.target_pc
.eq(Cat(0,
569 Mux(dc
.opcode
!= OP
.jalr
,
571 register_rs1
[1:32] + dc
.immediate
[1:32])))
573 misaligned_jump_target
= Signal()
574 self
.comb
+= misaligned_jump_target
.eq(ft
.target_pc
[1])
576 branch_arg_a
= Signal(32)
577 branch_arg_b
= Signal(32)
578 self
.comb
+= branch_arg_a
.eq(Cat( register_rs1
[0:31],
579 register_rs1
[31] ^ ~dc
.funct3
[1]))
580 self
.comb
+= branch_arg_b
.eq(Cat( register_rs2
[0:31],
581 register_rs2
[31] ^ ~dc
.funct3
[1]))
583 branch_taken
= Signal()
584 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
586 branch_arg_a
< branch_arg_b
,
587 branch_arg_a
== branch_arg_b
))
589 m
= M(self
.comb
, self
.sync
)
590 mstatus
= MStatus(self
.comb
, self
.sync
)
591 mie
= MIE(self
.comb
, self
.sync
)
593 misa
= Misa(self
.comb
, self
.sync
)
595 mvendorid
= Signal(32)
599 self
.comb
+= mvendorid
.eq(Constant(0, 32))
600 self
.comb
+= marchid
.eq(Constant(0, 32))
601 self
.comb
+= mimpid
.eq(Constant(0, 32))
602 self
.comb
+= mhartid
.eq(Constant(0, 32))
604 mip
= MIP(self
.comb
, self
.sync
)
606 csr_op_is_valid
= Signal()
608 self
.comb
+= ft
.get_fetch_action(dc
, load_store_misaligned
, mi
,
609 branch_taken
, misaligned_jump_target
,
612 #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
614 if __name__
== "__main__":
616 print(verilog
.convert(example
,
619 example
.tty_write_data
,
620 example
.tty_write_busy
,
629 wire [11:0] csr_number = decoder_immediate;
630 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
631 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
632 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
634 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
665 get_csr_op_is_valid = 0;
676 get_csr_op_is_valid = ~csr_writes;
685 get_csr_op_is_valid = 1;
692 // TODO: CSRs not implemented yet
693 get_csr_op_is_valid = 0;
698 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
700 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
701 wire [63:0] time_counter = 0; // TODO: implement time_counter
702 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
704 always @(posedge clk) begin:main_block
709 case(fetch_output_state)
710 `fetch_output_state_empty: begin
712 `fetch_output_state_trap: begin
715 `fetch_output_state_valid: begin:valid
716 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
719 else if((decode_action & `decode_action_load) != 0) begin
720 if(~memory_interface_rw_wait)
721 write_register(decoder_rd, loaded_value);
723 else if((decode_action & `decode_action_op_op_imm) != 0) begin
724 write_register(decoder_rd, alu_result);
726 else if((decode_action & `decode_action_lui_auipc) != 0) begin
727 write_register(decoder_rd, lui_auipc_result);
729 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
730 write_register(decoder_rd, fetch_output_pc + 4);
732 else if((decode_action & `decode_action_csr) != 0) begin:csr
733 reg [31:0] csr_output_value;
734 reg [31:0] csr_written_value;
735 csr_output_value = 32'hXXXXXXXX;
736 csr_written_value = 32'hXXXXXXXX;
739 csr_output_value = cycle_counter[31:0];
742 csr_output_value = time_counter[31:0];
745 csr_output_value = instret_counter[31:0];
748 csr_output_value = cycle_counter[63:32];
751 csr_output_value = time_counter[63:32];
754 csr_output_value = instret_counter[63:32];
756 `csr_mvendorid: begin
757 csr_output_value = mvendorid;
760 csr_output_value = marchid;
763 csr_output_value = mimpid;
766 csr_output_value = mhartid;
769 csr_output_value = misa;
772 csr_output_value = make_mstatus(mstatus_tsr,
788 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
790 mstatus_mpie = csr_written_value[7];
791 mstatus_mie = csr_written_value[3];
795 csr_output_value = 0;
796 csr_output_value[11] = mie_meie;
797 csr_output_value[9] = mie_seie;
798 csr_output_value[8] = mie_ueie;
799 csr_output_value[7] = mie_mtie;
800 csr_output_value[5] = mie_stie;
801 csr_output_value[4] = mie_utie;
802 csr_output_value[3] = mie_msie;
803 csr_output_value[1] = mie_ssie;
804 csr_output_value[0] = mie_usie;
805 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
807 mie_meie = csr_written_value[11];
808 mie_mtie = csr_written_value[7];
809 mie_msie = csr_written_value[3];
813 csr_output_value = mtvec;
816 csr_output_value = mscratch;
817 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
819 mscratch = csr_written_value;
822 csr_output_value = mepc;
823 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
825 mepc = csr_written_value;
828 csr_output_value = mcause;
829 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
831 mcause = csr_written_value;
834 csr_output_value = 0;
835 csr_output_value[11] = mip_meip;
836 csr_output_value[9] = mip_seip;
837 csr_output_value[8] = mip_ueip;
838 csr_output_value[7] = mip_mtip;
839 csr_output_value[5] = mip_stip;
840 csr_output_value[4] = mip_utip;
841 csr_output_value[3] = mip_msip;
842 csr_output_value[1] = mip_ssip;
843 csr_output_value[0] = mip_usip;
847 write_register(decoder_rd, csr_output_value);
849 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin