3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
62 def __init__(self
, comb
, sync
):
65 self
.mpie
= Signal(name
="mstatus_mpie")
66 self
.mie
= Signal(name
="mstatus_mie")
67 self
.mprv
= Signal(name
="mstatus_mprv")
68 self
.tsr
= Signal(name
="mstatus_tsr")
69 self
.tw
= Signal(name
="mstatus_tw")
70 self
.tvm
= Signal(name
="mstatus_tvm")
71 self
.mxr
= Signal(name
="mstatus_mxr")
72 self
._sum
= Signal(name
="mstatus_sum")
73 self
.xs
= Signal(name
="mstatus_xs")
74 self
.fs
= Signal(name
="mstatus_fs")
75 self
.mpp
= Signal(2, name
="mstatus_mpp")
76 self
.spp
= Signal(name
="mstatus_spp")
77 self
.spie
= Signal(name
="mstatus_spie")
78 self
.upie
= Signal(name
="mstatus_upie")
79 self
.sie
= Signal(name
="mstatus_sie")
80 self
.uie
= Signal(name
="mstatus_uie")
83 if n
in ['make', 'mpp', 'comb', 'sync'] or n
.startswith("_"):
85 self
.comb
+= getattr(self
, n
).eq(0x0)
86 self
.comb
+= self
.mpp
.eq(0b11)
88 self
.sync
+= self
.mie
.eq(0)
89 self
.sync
+= self
.mpie
.eq(0)
93 self
.uie
, self
.sie
, Constant(0), self
.mie
,
94 self
.upie
, self
.spie
, Constant(0), self
.mpie
,
95 self
.spp
, Constant(0, 2), self
.mpp
,
96 self
.fs
, self
.xs
, self
.mprv
, self
._sum
,
97 self
.mxr
, self
.tvm
, self
.tw
, self
.tsr
,
99 (self
.xs
== Constant(0b11, 2)) |
(self
.fs
== Constant(0b11, 2))
104 def __init__(self
, comb
, sync
):
107 self
.meie
= Signal(name
="mie_meie")
108 self
.mtie
= Signal(name
="mie_mtie")
109 self
.msie
= Signal(name
="mie_msie")
110 self
.ueie
= Signal(name
="mie_ueie")
111 self
.stie
= Signal(name
="mie_stie")
112 self
.utie
= Signal(name
="mie_utie")
113 self
.ssie
= Signal(name
="mie_ssie")
114 self
.usie
= Signal(name
="mie_usie")
117 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
119 self
.comb
+= getattr(self
, n
).eq(0x0)
121 self
.sync
+= self
.meie
.eq(0)
122 self
.sync
+= self
.mtie
.eq(0)
123 self
.sync
+= self
.msie
.eq(0)
126 def __init__(self
, comb
, sync
):
129 self
.meip
= Signal(name
="mip_meip") # TODO: implement ext interrupts
130 self
.seip
= Signal(name
="mip_seip")
131 self
.ueip
= Signal(name
="mip_uiep")
132 self
.mtip
= Signal(name
="mip_mtip") # TODO: implement timer interrupts
133 self
.stip
= Signal(name
="mip_stip")
134 self
.msip
= Signal(name
="mip_stip")
135 self
.utip
= Signal(name
="mip_utip")
136 self
.ssip
= Signal(name
="mip_ssip")
137 self
.usip
= Signal(name
="mip_usip")
140 if n
in ['comb', 'sync'] or n
.startswith("_"):
142 self
.comb
+= getattr(self
, n
).eq(0x0)
146 def __init__(self
, comb
, sync
):
149 self
.mcause
= Signal(32)
150 self
.mepc
= Signal(32)
151 self
.mscratch
= Signal(32)
152 self
.sync
+= self
.mcause
.eq(0)
153 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
154 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
157 def __init__(self
, comb
, sync
):
160 self
.misa
= Signal(32)
162 for l
in list(string
.ascii_lowercase
):
163 value
= 1 if l
== 'i' else 0
164 cl
.append(Constant(value
))
165 cl
.append(Constant(0, 4))
166 cl
.append(Constant(0b01, 2))
167 self
.comb
+= self
.misa
.eq(Cat(cl
))
171 def __init__(self
, comb
, sync
):
174 self
.action
= Signal(fetch_action
, name
="fetch_action")
175 self
.target_pc
= Signal(32, name
="fetch_target_pc")
176 self
.output_pc
= Signal(32, name
="fetch_output_pc")
177 self
.output_instruction
= Signal(32, name
="fetch_ouutput_instruction")
178 self
.output_state
= Signal(fetch_output_state
,name
="fetch_output_state")
180 def get_fetch_action(self
, dc
, load_store_misaligned
, mi
,
181 branch_taken
, misaligned_jump_target
,
184 c
["default"] = self
.action
.eq(FA
.default
) # XXX should be 32'XXXXXXXX?
185 c
[FOS
.empty
] = self
.action
.eq(FA
.default
)
186 c
[FOS
.trap
] = self
.action
.eq(FA
.ack_trap
)
188 # illegal instruction -> error trap
189 i
= If((dc
.act
& DA
.trap_illegal_instruction
) != 0,
190 self
.action
.eq(FA
.error_trap
)
193 # ecall / ebreak -> noerror trap
194 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
195 self
.action
.eq(FA
.noerror_trap
))
197 # load/store: check alignment, check wait
198 i
= i
.Elif((dc
.act
& (DA
.load | DA
.store
)) != 0,
199 If((load_store_misaligned | ~mi
.rw_address_valid
),
200 self
.action
.eq(FA
.error_trap
) # misaligned or invalid addr
202 self
.action
.eq(FA
.wait
) # wait
204 self
.action
.eq(FA
.default
) # ok
209 i
= i
.Elif((dc
.act
& DA
.fence
) != 0,
210 self
.action
.eq(FA
.fence
))
212 # branch -> misaligned=error, otherwise jump
213 i
= i
.Elif((dc
.act
& DA
.branch
) != 0,
214 If(misaligned_jump_target
,
215 self
.action
.eq(FA
.error_trap
)
217 self
.action
.eq(FA
.jump
)
221 # jal/jalr -> misaligned=error, otherwise jump
222 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
223 If(misaligned_jump_target
,
224 self
.action
.eq(FA
.error_trap
)
226 self
.action
.eq(FA
.jump
)
230 # csr -> opvalid=ok, else error trap
231 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
233 self
.action
.eq(FA
.default
)
235 self
.action
.eq(FA
.error_trap
)
241 return Case(self
.output_state
, c
)
248 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
249 return Case(funct3
[:2],
250 { F3
.sb
: ls
.eq(Constant(0)),
251 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
252 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
253 "default": ls
.eq(Constant(1))
256 def get_lsbm(self
, dc
):
257 return Cat(Constant(1),
258 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
259 Constant(1), Constant(0)),
261 Constant(0b11, 2), Constant(0, 2)))
263 # XXX this happens to get done by various self.sync actions
264 #def reset_to_initial(self, m, mstatus, mie, registers):
265 # return [m.mcause.eq(0),
268 def write_register(self
, register_number
, value
):
269 return If(register_number
!= 0,
270 self
.registers
[register_number
].eq(value
)
273 def evaluate_csr_funct3_op(self
, funct3
, previous_value
, written_value
):
274 c
= { "default": Constant(0, 32)}
275 for f
in [F3
.csrrw
, F3
.csrrwi
]: c
[f
] = written_value
276 for f
in [F3
.csrrs
, F3
.csrrsi
]: c
[f
] = written_value | previous_value
277 for f
in [F3
.csrrc
, F3
.csrrci
]: c
[f
] = ~written_value
& previous_value
278 return Case(funct3
, c
)
281 self
.clk
= ClockSignal()
282 self
.reset
= ResetSignal()
283 self
.tty_write
= Signal()
284 self
.tty_write_data
= Signal(8)
285 self
.tty_write_busy
= Signal()
286 self
.switch_2
= Signal()
287 self
.switch_3
= Signal()
288 self
.led_1
= Signal()
289 self
.led_3
= Signal()
291 ram_size
= Constant(0x8000)
292 ram_start
= Constant(0x10000, 32)
293 reset_vector
= Signal(32)
296 reset_vector
.eq(ram_start
)
297 mtvec
.eq(ram_start
+ 0x40)
301 r
= Signal(32, name
="register%d" % i
)
303 self
.sync
+= r
.eq(Constant(0, 32))
304 self
.registers
= Array(l
)
306 mi
= MemoryInterface()
308 mii
= Instance("cpu_memory_interface", name
="memory_instance",
309 p_ram_size
= ram_size
,
310 p_ram_start
= ram_start
,
313 i_fetch_address
= mi
.fetch_address
,
314 o_fetch_data
= mi
.fetch_data
,
315 o_fetch_valid
= mi
.fetch_valid
,
316 i_rw_address
= mi
.rw_address
,
317 i_rw_byte_mask
= mi
.rw_byte_mask
,
318 i_rw_read_not_write
= mi
.rw_read_not_write
,
319 i_rw_active
= mi
.rw_active
,
320 i_rw_data_in
= mi
.rw_data_in
,
321 o_rw_data_out
= mi
.rw_data_out
,
322 o_rw_address_valid
= mi
.rw_address_valid
,
323 o_rw_wait
= mi
.rw_wait
,
324 o_tty_write
= self
.tty_write
,
325 o_tty_write_data
= self
.tty_write_data
,
326 i_tty_write_busy
= self
.tty_write_busy
,
327 i_switch_2
= self
.switch_2
,
328 i_switch_3
= self
.switch_3
,
329 o_led_1
= self
.led_1
,
334 ft
= Fetch(self
.comb
, self
.sync
)
336 fs
= Instance("CPUFetchStage", name
="fetch_stage",
339 o_memory_interface_fetch_address
= mi
.fetch_address
,
340 i_memory_interface_fetch_data
= mi
.fetch_data
,
341 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
342 i_fetch_action
= ft
.action
,
343 i_target_pc
= ft
.target_pc
,
344 o_output_pc
= ft
.output_pc
,
345 o_output_instruction
= ft
.output_instruction
,
346 o_output_state
= ft
.output_state
,
347 i_reset_vector
= reset_vector
,
354 cd
= Instance("CPUDecoder", name
="decoder",
355 i_instruction
= ft
.output_instruction
,
356 o_funct7
= dc
.funct7
,
357 o_funct3
= dc
.funct3
,
361 o_immediate
= dc
.immediate
,
362 o_opcode
= dc
.opcode
,
363 o_decode_action
= dc
.act
367 register_rs1
= Signal(32)
368 register_rs2
= Signal(32)
369 self
.comb
+= If(dc
.rs1
== 0,
372 register_rs1
.eq(self
.registers
[dc
.rs1
-1]))
373 self
.comb
+= If(dc
.rs2
== 0,
376 register_rs2
.eq(self
.registers
[dc
.rs2
-1]))
378 load_store_address
= Signal(32)
379 load_store_address_low_2
= Signal(2)
381 self
.comb
+= load_store_address
.eq(dc
.immediate
+ register_rs1
)
382 self
.comb
+= load_store_address_low_2
.eq(
383 dc
.immediate
[:2] + register_rs1
[:2])
385 load_store_misaligned
= Signal()
387 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
388 load_store_address_low_2
)
391 # XXX rwaddr not 31:2 any more
392 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
394 unshifted_load_store_byte_mask
= Signal(4)
396 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
398 # XXX yuck. this will cause migen simulation to fail
399 # (however conversion to verilog works)
400 self
.comb
+= mi
.rw_byte_mask
.eq(
401 _Operator("<<", [unshifted_load_store_byte_mask
,
402 load_store_address_low_2
]))
405 b3
= Mux(load_store_address_low_2
[1],
406 Mux(load_store_address_low_2
[0], register_rs2
[0:8],
408 Mux(load_store_address_low_2
[0], register_rs2
[16:24],
409 register_rs2
[24:32]))
410 b2
= Mux(load_store_address_low_2
[1], register_rs2
[0:8],
412 b1
= Mux(load_store_address_low_2
[0], register_rs2
[0:8],
414 b0
= register_rs2
[0:8]
416 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
419 unmasked_loaded_value
= Signal(32)
421 b0
= Mux(load_store_address_low_2
[1],
422 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
423 mi
.rw_data_out
[16:24]),
424 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
425 mi
.rw_data_out
[0:8]))
426 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
427 mi
.rw_data_out
[8:16])
428 b23
= mi
.rw_data_out
[16:32]
430 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
433 loaded_value
= Signal(32)
435 b0
= unmasked_loaded_value
[0:8]
436 b1
= Mux(dc
.funct3
[0:2] == 0,
437 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
438 unmasked_loaded_value
[8:16])
439 b2
= Mux(dc
.funct3
[1] == 0,
440 Replicate(~dc
.funct3
[2] &
441 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
442 unmasked_loaded_value
[7]),
444 unmasked_loaded_value
[16:32])
446 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
448 self
.comb
+= mi
.rw_active
.eq(~self
.reset
449 & (ft
.output_state
== FOS
.valid
)
450 & ~load_store_misaligned
451 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
453 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
458 alu_result
= Signal(32)
460 self
.comb
+= alu_a
.eq(register_rs1
)
461 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
465 ali
= Instance("cpu_alu", name
="alu",
466 i_funct7
= dc
.funct7
,
467 i_funct3
= dc
.funct3
,
468 i_opcode
= dc
.opcode
,
471 o_result
= alu_result
475 lui_auipc_result
= Signal(32)
476 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
478 dc
.immediate
+ ft
.output_pc
))
480 self
.comb
+= ft
.target_pc
.eq(Cat(0,
481 Mux(dc
.opcode
!= OP
.jalr
,
483 register_rs1
[1:32] + dc
.immediate
[1:32])))
485 misaligned_jump_target
= Signal()
486 self
.comb
+= misaligned_jump_target
.eq(ft
.target_pc
[1])
488 branch_arg_a
= Signal(32)
489 branch_arg_b
= Signal(32)
490 self
.comb
+= branch_arg_a
.eq(Cat( register_rs1
[0:31],
491 register_rs1
[31] ^ ~dc
.funct3
[1]))
492 self
.comb
+= branch_arg_b
.eq(Cat( register_rs2
[0:31],
493 register_rs2
[31] ^ ~dc
.funct3
[1]))
495 branch_taken
= Signal()
496 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
498 branch_arg_a
< branch_arg_b
,
499 branch_arg_a
== branch_arg_b
))
501 m
= M(self
.comb
, self
.sync
)
502 mstatus
= MStatus(self
.comb
, self
.sync
)
503 mie
= MIE(self
.comb
, self
.sync
)
505 misa
= Misa(self
.comb
, self
.sync
)
507 mvendorid
= Signal(32)
511 self
.comb
+= mvendorid
.eq(Constant(0, 32))
512 self
.comb
+= marchid
.eq(Constant(0, 32))
513 self
.comb
+= mimpid
.eq(Constant(0, 32))
514 self
.comb
+= mhartid
.eq(Constant(0, 32))
516 mip
= MIP(self
.comb
, self
.sync
)
518 csr_op_is_valid
= Signal()
520 self
.comb
+= ft
.get_fetch_action(dc
, load_store_misaligned
, mi
,
521 branch_taken
, misaligned_jump_target
,
523 if __name__
== "__main__":
525 print(verilog
.convert(example
,
528 example
.tty_write_data
,
529 example
.tty_write_busy
,
538 function `fetch_action get_fetch_action(
539 input `fetch_output_state fetch_output_state,
540 input `decode_action decode_action,
541 input load_store_misaligned,
542 input memory_interface_rw_address_valid,
543 input memory_interface_rw_wait,
545 input misaligned_jump_target,
546 input csr_op_is_valid
549 case(fetch_output_state)
550 `fetch_output_state_empty:
551 get_fetch_action = `fetch_action_default;
552 `fetch_output_state_trap:
553 get_fetch_action = `fetch_action_ack_trap;
554 `fetch_output_state_valid: begin
555 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
556 get_fetch_action = `fetch_action_error_trap;
558 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
559 get_fetch_action = `fetch_action_noerror_trap;
561 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
562 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
563 get_fetch_action = `fetch_action_error_trap;
565 else if(memory_interface_rw_wait) begin
566 get_fetch_action = `fetch_action_wait;
569 get_fetch_action = `fetch_action_default;
572 else if((decode_action & `decode_action_fence_i) != 0) begin
573 get_fetch_action = `fetch_action_fence;
575 else if((decode_action & `decode_action_branch) != 0) begin
576 if(branch_taken) begin
577 if(misaligned_jump_target) begin
578 get_fetch_action = `fetch_action_error_trap;
581 get_fetch_action = `fetch_action_jump;
586 get_fetch_action = `fetch_action_default;
589 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
590 if(misaligned_jump_target) begin
591 get_fetch_action = `fetch_action_error_trap;
594 get_fetch_action = `fetch_action_jump;
597 else if((decode_action & `decode_action_csr) != 0) begin
599 get_fetch_action = `fetch_action_default;
601 get_fetch_action = `fetch_action_error_trap;
604 get_fetch_action = `fetch_action_default;
608 get_fetch_action = 32'hXXXXXXXX;
613 assign fetch_action = get_fetch_action(
616 load_store_misaligned,
617 memory_interface_rw_address_valid,
618 memory_interface_rw_wait,
620 misaligned_jump_target,
626 mstatus_mpie = mstatus_mie;
628 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
629 if(fetch_action == `fetch_action_ack_trap) begin
630 mcause = `cause_instruction_access_fault;
632 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
633 mcause = `cause_illegal_instruction;
635 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
636 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
638 else if((decode_action & `decode_action_load) != 0) begin
639 if(load_store_misaligned)
640 mcause = `cause_load_address_misaligned;
642 mcause = `cause_load_access_fault;
644 else if((decode_action & `decode_action_store) != 0) begin
645 if(load_store_misaligned)
646 mcause = `cause_store_amo_address_misaligned;
648 mcause = `cause_store_amo_access_fault;
650 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
651 mcause = `cause_instruction_address_misaligned;
654 mcause = `cause_illegal_instruction;
659 wire [11:0] csr_number = decoder_immediate;
660 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
661 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
662 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
664 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
695 get_csr_op_is_valid = 0;
706 get_csr_op_is_valid = ~csr_writes;
715 get_csr_op_is_valid = 1;
722 // TODO: CSRs not implemented yet
723 get_csr_op_is_valid = 0;
728 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
730 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
731 wire [63:0] time_counter = 0; // TODO: implement time_counter
732 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
734 always @(posedge clk) begin:main_block
739 case(fetch_output_state)
740 `fetch_output_state_empty: begin
742 `fetch_output_state_trap: begin
745 `fetch_output_state_valid: begin:valid
746 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
749 else if((decode_action & `decode_action_load) != 0) begin
750 if(~memory_interface_rw_wait)
751 write_register(decoder_rd, loaded_value);
753 else if((decode_action & `decode_action_op_op_imm) != 0) begin
754 write_register(decoder_rd, alu_result);
756 else if((decode_action & `decode_action_lui_auipc) != 0) begin
757 write_register(decoder_rd, lui_auipc_result);
759 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
760 write_register(decoder_rd, fetch_output_pc + 4);
762 else if((decode_action & `decode_action_csr) != 0) begin:csr
763 reg [31:0] csr_output_value;
764 reg [31:0] csr_written_value;
765 csr_output_value = 32'hXXXXXXXX;
766 csr_written_value = 32'hXXXXXXXX;
769 csr_output_value = cycle_counter[31:0];
772 csr_output_value = time_counter[31:0];
775 csr_output_value = instret_counter[31:0];
778 csr_output_value = cycle_counter[63:32];
781 csr_output_value = time_counter[63:32];
784 csr_output_value = instret_counter[63:32];
786 `csr_mvendorid: begin
787 csr_output_value = mvendorid;
790 csr_output_value = marchid;
793 csr_output_value = mimpid;
796 csr_output_value = mhartid;
799 csr_output_value = misa;
802 csr_output_value = make_mstatus(mstatus_tsr,
818 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
820 mstatus_mpie = csr_written_value[7];
821 mstatus_mie = csr_written_value[3];
825 csr_output_value = 0;
826 csr_output_value[11] = mie_meie;
827 csr_output_value[9] = mie_seie;
828 csr_output_value[8] = mie_ueie;
829 csr_output_value[7] = mie_mtie;
830 csr_output_value[5] = mie_stie;
831 csr_output_value[4] = mie_utie;
832 csr_output_value[3] = mie_msie;
833 csr_output_value[1] = mie_ssie;
834 csr_output_value[0] = mie_usie;
835 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
837 mie_meie = csr_written_value[11];
838 mie_mtie = csr_written_value[7];
839 mie_msie = csr_written_value[3];
843 csr_output_value = mtvec;
846 csr_output_value = mscratch;
847 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
849 mscratch = csr_written_value;
852 csr_output_value = mepc;
853 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
855 mepc = csr_written_value;
858 csr_output_value = mcause;
859 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
861 mcause = csr_written_value;
864 csr_output_value = 0;
865 csr_output_value[11] = mip_meip;
866 csr_output_value[9] = mip_seip;
867 csr_output_value[8] = mip_ueip;
868 csr_output_value[7] = mip_mtip;
869 csr_output_value[5] = mip_stip;
870 csr_output_value[4] = mip_utip;
871 csr_output_value[3] = mip_msip;
872 csr_output_value[1] = mip_ssip;
873 csr_output_value[0] = mip_usip;
877 write_register(decoder_rd, csr_output_value);
879 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin