3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
62 def __init__(self
, comb
, sync
):
65 self
.mpie
= Signal(name
="mstatus_mpie")
66 self
.mie
= Signal(name
="mstatus_mie")
67 self
.mprv
= Signal(name
="mstatus_mprv")
68 self
.tsr
= Signal(name
="mstatus_tsr")
69 self
.tw
= Signal(name
="mstatus_tw")
70 self
.tvm
= Signal(name
="mstatus_tvm")
71 self
.mxr
= Signal(name
="mstatus_mxr")
72 self
._sum
= Signal(name
="mstatus_sum")
73 self
.xs
= Signal(name
="mstatus_xs")
74 self
.fs
= Signal(name
="mstatus_fs")
75 self
.mpp
= Signal(2, name
="mstatus_mpp")
76 self
.spp
= Signal(name
="mstatus_spp")
77 self
.spie
= Signal(name
="mstatus_spie")
78 self
.upie
= Signal(name
="mstatus_upie")
79 self
.sie
= Signal(name
="mstatus_sie")
80 self
.uie
= Signal(name
="mstatus_uie")
83 if n
in ['make', 'mpp', 'comb', 'sync'] or n
.startswith("_"):
85 self
.comb
+= getattr(self
, n
).eq(0x0)
86 self
.comb
+= self
.mpp
.eq(0b11)
88 self
.sync
+= self
.mie
.eq(0)
89 self
.sync
+= self
.mpie
.eq(0)
93 self
.uie
, self
.sie
, Constant(0), self
.mie
,
94 self
.upie
, self
.spie
, Constant(0), self
.mpie
,
95 self
.spp
, Constant(0, 2), self
.mpp
,
96 self
.fs
, self
.xs
, self
.mprv
, self
._sum
,
97 self
.mxr
, self
.tvm
, self
.tw
, self
.tsr
,
99 (self
.xs
== Constant(0b11, 2)) |
(self
.fs
== Constant(0b11, 2))
104 def __init__(self
, comb
, sync
):
107 self
.meie
= Signal(name
="mie_meie")
108 self
.mtie
= Signal(name
="mie_mtie")
109 self
.msie
= Signal(name
="mie_msie")
110 self
.seie
= Signal(name
="mie_seie")
111 self
.ueie
= Signal(name
="mie_ueie")
112 self
.stie
= Signal(name
="mie_stie")
113 self
.utie
= Signal(name
="mie_utie")
114 self
.ssie
= Signal(name
="mie_ssie")
115 self
.usie
= Signal(name
="mie_usie")
118 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
120 self
.comb
+= getattr(self
, n
).eq(0x0)
122 self
.sync
+= self
.meie
.eq(0)
123 self
.sync
+= self
.mtie
.eq(0)
124 self
.sync
+= self
.msie
.eq(0)
127 return Cat( self
.usie
, self
.ssie
, 0, self
.msie
,
128 self
.utie
, self
.stie
, 0, self
.mtie
,
129 self
.ueie
, self
.seie
, 0, self
.meie
, )
133 def __init__(self
, comb
, sync
):
136 self
.meip
= Signal(name
="mip_meip") # TODO: implement ext interrupts
137 self
.seip
= Signal(name
="mip_seip")
138 self
.ueip
= Signal(name
="mip_uiep")
139 self
.mtip
= Signal(name
="mip_mtip") # TODO: implement timer interrupts
140 self
.stip
= Signal(name
="mip_stip")
141 self
.msip
= Signal(name
="mip_stip")
142 self
.utip
= Signal(name
="mip_utip")
143 self
.ssip
= Signal(name
="mip_ssip")
144 self
.usip
= Signal(name
="mip_usip")
147 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
149 self
.comb
+= getattr(self
, n
).eq(0x0)
152 return Cat( self
.usip
, self
.ssip
, 0, self
.msip
,
153 self
.utip
, self
.stip
, 0, self
.mtip
,
154 self
.ueip
, self
.seip
, 0, self
.meip
, )
158 def __init__(self
, comb
, sync
):
161 self
.mcause
= Signal(32)
162 self
.mepc
= Signal(32)
163 self
.mscratch
= Signal(32)
164 self
.sync
+= self
.mcause
.eq(0)
165 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
166 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
170 def __init__(self
, comb
, sync
):
173 self
.misa
= Signal(32)
175 for l
in list(string
.ascii_lowercase
):
176 value
= 1 if l
== 'i' else 0
177 cl
.append(Constant(value
))
178 cl
.append(Constant(0, 4))
179 cl
.append(Constant(0b01, 2))
180 self
.comb
+= self
.misa
.eq(Cat(cl
))
184 def __init__(self
, comb
, sync
):
187 self
.action
= Signal(fetch_action
, name
="fetch_action")
188 self
.target_pc
= Signal(32, name
="fetch_target_pc")
189 self
.output_pc
= Signal(32, name
="fetch_output_pc")
190 self
.output_instruction
= Signal(32, name
="fetch_ouutput_instruction")
191 self
.output_state
= Signal(fetch_output_state
,name
="fetch_output_state")
193 def get_fetch_action(self
, dc_act
, load_store_misaligned
, mi_rw_wait
,
195 branch_taken
, misaligned_jump_target
,
198 c
["default"] = self
.action
.eq(FA
.default
) # XXX should be 32'XXXXXXXX?
199 c
[FOS
.empty
] = self
.action
.eq(FA
.default
)
200 c
[FOS
.trap
] = self
.action
.eq(FA
.ack_trap
)
202 # illegal instruction -> error trap
203 i
= If((dc_act
& DA
.trap_illegal_instruction
) != 0,
204 self
.action
.eq(FA
.error_trap
)
207 # ecall / ebreak -> noerror trap
208 i
= i
.Elif((dc_act
& DA
.trap_ecall_ebreak
) != 0,
209 self
.action
.eq(FA
.noerror_trap
))
211 # load/store: check alignment, check wait
212 i
= i
.Elif((dc_act
& (DA
.load | DA
.store
)) != 0,
213 If((load_store_misaligned | ~mi_rw_address_valid
),
214 self
.action
.eq(FA
.error_trap
) # misaligned or invalid addr
216 self
.action
.eq(FA
.wait
) # wait
218 self
.action
.eq(FA
.default
) # ok
223 i
= i
.Elif((dc_act
& DA
.fence
) != 0,
224 self
.action
.eq(FA
.fence
))
226 # branch -> misaligned=error, otherwise jump
227 i
= i
.Elif((dc_act
& DA
.branch
) != 0,
229 If(misaligned_jump_target
,
230 self
.action
.eq(FA
.error_trap
)
232 self
.action
.eq(FA
.jump
)
235 self
.action
.eq(FA
.default
)
239 # jal/jalr -> misaligned=error, otherwise jump
240 i
= i
.Elif((dc_act
& (DA
.jal | DA
.jalr
)) != 0,
241 If(misaligned_jump_target
,
242 self
.action
.eq(FA
.error_trap
)
244 self
.action
.eq(FA
.jump
)
248 # csr -> opvalid=ok, else error trap
249 i
= i
.Elif((dc_act
& DA
.csr
) != 0,
251 self
.action
.eq(FA
.default
)
253 self
.action
.eq(FA
.error_trap
)
259 return Case(self
.output_state
, c
)
262 def __init__(self
, comb
, sync
, dc
, register_rs1
):
265 self
.number
= Signal(12, name
="csr_number")
266 self
.input_value
= Signal(32, name
="csr_input_value")
267 self
.reads
= Signal(name
="csr_reads")
268 self
.writes
= Signal(name
="csr_writes")
269 self
.op_is_valid
= Signal(name
="csr_op_is_valid")
271 self
.comb
+= self
.number
.eq(dc
.immediate
)
272 self
.comb
+= self
.input_value
.eq(Mux(dc
.funct3
[2],
275 self
.comb
+= self
.reads
.eq(dc
.funct3
[1] |
(dc
.rd
!= 0))
276 self
.comb
+= self
.writes
.eq(~dc
.funct3
[1] |
(dc
.rs1
!= 0))
278 self
.comb
+= self
.get_csr_op_is_valid()
280 def get_csr_op_is_valid(self
):
281 """ determines if a CSR is valid
285 for f
in [csr_ustatus
, csr_fflags
, csr_frm
, csr_fcsr
,
286 csr_uie
, csr_utvec
, csr_uscratch
, csr_uepc
,
287 csr_ucause
, csr_utval
, csr_uip
, csr_sstatus
,
288 csr_sedeleg
, csr_sideleg
, csr_sie
, csr_stvec
,
289 csr_scounteren
, csr_sscratch
, csr_sepc
, csr_scause
,
290 csr_stval
, csr_sip
, csr_satp
, csr_medeleg
,
291 csr_mideleg
, csr_dcsr
, csr_dpc
, csr_dscratch
]:
292 c
[f
] = self
.op_is_valid
.eq(0)
294 # not-writeable -> ok
295 for f
in [csr_cycle
, csr_time
, csr_instret
, csr_cycleh
,
296 csr_timeh
, csr_instreth
, csr_mvendorid
, csr_marchid
,
297 csr_mimpid
, csr_mhartid
]:
298 c
[f
] = self
.op_is_valid
.eq(~self
.writes
)
301 for f
in [csr_misa
, csr_mstatus
, csr_mie
, csr_mtvec
,
302 csr_mscratch
, csr_mepc
, csr_mcause
, csr_mip
]:
303 c
[f
] = self
.op_is_valid
.eq(1)
305 # not implemented / default
306 for f
in [csr_mcounteren
, csr_mtval
, csr_mcycle
, csr_minstret
,
307 csr_mcycleh
, csr_minstreth
, "default"]:
308 c
[f
] = self
.op_is_valid
.eq(0)
310 return Case(self
.number
, c
)
312 def evaluate_csr_funct3_op(self
, funct3
, previous
, written
):
313 c
= { "default": written
.eq(Constant(0, 32))}
314 for f
in [F3
.csrrw
, F3
.csrrwi
]:
315 c
[f
] = written
.eq(self
.input_value
)
316 for f
in [F3
.csrrs
, F3
.csrrsi
]:
317 c
[f
] = written
.eq(self
.input_value | previous
)
318 for f
in [F3
.csrrc
, F3
.csrrci
]:
319 c
[f
] = written
.eq(~self
.input_value
& previous
)
320 return Case(funct3
, c
)
324 def __init__(self
, comb
):
327 self
.cycle_counter
= Signal(64); # TODO: implement cycle_counter
328 self
.time_counter
= Signal(64); # TODO: implement time_counter
329 self
.instret_counter
= Signal(64); # TODO: implement instret_counter
331 self
.mvendorid
= Signal(32)
332 self
.marchid
= Signal(32)
333 self
.mimpid
= Signal(32)
334 self
.mhartid
= Signal(32)
335 self
.comb
+= self
.mvendorid
.eq(Constant(0, 32))
336 self
.comb
+= self
.marchid
.eq(Constant(0, 32))
337 self
.comb
+= self
.mimpid
.eq(Constant(0, 32))
338 self
.comb
+= self
.mhartid
.eq(Constant(0, 32))
341 def __init__(self
, comb
, sync
):
345 self
.ra_en
= Signal(reset
=1, name
="regfile_ra_en") # TODO: ondemand en
346 self
.rs1
= Signal(32, name
="regfile_rs1")
347 self
.rs_a
= Signal(5, name
="regfile_rs_a")
349 self
.rb_en
= Signal(reset
=1, name
="regfile_rb_en") # TODO: ondemand en
350 self
.rs2
= Signal(32, name
="regfile_rs2")
351 self
.rs_b
= Signal(5, name
="regfile_rs_b")
353 self
.w_en
= Signal(name
="regfile_w_en")
354 self
.wval
= Signal(32, name
="regfile_wval")
355 self
.rd
= Signal(32, name
="regfile_rd")
361 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
362 """ returns whether a load/store is misaligned
364 return Case(funct3
[:2],
365 { F3
.sb
: ls
.eq(Constant(0)),
366 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
367 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
368 "default": ls
.eq(Constant(1))
371 def get_lsbm(self
, dc
):
372 return Cat(Constant(1),
373 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
374 Constant(1), Constant(0)),
376 Constant(0b11, 2), Constant(0, 2)))
378 # XXX this happens to get done by various self.sync actions
379 #def reset_to_initial(self, m, mstatus, mie, registers):
380 # return [m.mcause.eq(0),
383 def handle_trap(self
, m
, ms
, ft
, dc
, load_store_misaligned
):
384 s
= [ms
.mpie
.eq(ms
.mie
),
386 m
.mepc
.eq(Mux(ft
.action
== FA
.noerror_trap
,
390 # fetch action ack trap
391 i
= If(ft
.action
== FA
.ack_trap
,
392 m
.mcause
.eq(cause_instruction_access_fault
)
396 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
397 m
.mcause
.eq(Mux(dc
.immediate
[0],
398 cause_machine_environment_call
,
403 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
404 If(load_store_misaligned
,
405 m
.mcause
.eq(cause_load_address_misaligned
)
407 m
.mcause
.eq(cause_load_access_fault
)
412 i
= i
.Elif((dc
.act
& DA
.store
) != 0,
413 If(load_store_misaligned
,
414 m
.mcause
.eq(cause_store_amo_address_misaligned
)
416 m
.mcause
.eq(cause_store_amo_access_fault
)
420 # jal/jalr -> misaligned=error, otherwise jump
421 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr | DA
.branch
)) != 0,
422 m
.mcause
.eq(cause_instruction_address_misaligned
)
425 # defaults to illegal instruction
426 i
= i
.Else(m
.mcause
.eq(cause_illegal_instruction
))
431 def main_block(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
433 load_store_misaligned
,
434 loaded_value
, alu_result
,
438 c
[FOS
.trap
] = self
.handle_trap(m
, mstatus
, ft
, dc
,
439 load_store_misaligned
)
440 c
[FOS
.valid
] = self
.handle_valid(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
441 mstatus
, mie
, ft
, dc
,
442 load_store_misaligned
,
446 return Case(ft
.output_state
, c
)
448 def write_register(self
, rd
, val
):
449 return [self
.regs
.rd
.eq(rd
),
450 self
.regs
.wval
.eq(val
),
454 def handle_valid(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
456 load_store_misaligned
,
457 loaded_value
, alu_result
,
459 # fetch action ack trap
460 i
= If((ft
.action
== FA
.ack_trap
) |
(ft
.action
== FA
.noerror_trap
),
461 [self
.handle_trap(m
, mstatus
, ft
, dc
,
462 load_store_misaligned
),
463 self
.regs
.w_en
.eq(0) # no writing to registers
468 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
470 self
.write_register(dc
.rd
, loaded_value
)
475 i
= i
.Elif((dc
.act
& DA
.op_op_imm
) != 0,
476 self
.write_register(dc
.rd
, alu_result
)
480 i
= i
.Elif((dc
.act
& DA
.lui_auipc
) != 0,
481 self
.write_register(dc
.rd
, lui_auipc_result
)
485 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
486 self
.write_register(dc
.rd
, ft
.output_pc
+ 4)
489 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
490 self
.handle_csr(mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
,
494 # fence, store, branch
495 i
= i
.Elif((dc
.act
& (DA
.fence | DA
.fence_i |
496 DA
.store | DA
.branch
)) != 0,
498 self
.regs
.w_en
.eq(0) # no writing to registers
503 def handle_csr(self
, mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
, dc
, csr
):
504 csr_output_value
= Signal(32)
505 csr_written_value
= Signal(32)
509 c
[csr_cycle
] = csr_output_value
.eq(minfo
.cycle_counter
[0:32])
510 c
[csr_cycleh
] = csr_output_value
.eq(minfo
.cycle_counter
[32:64])
512 c
[csr_time
] = csr_output_value
.eq(minfo
.time_counter
[0:32])
513 c
[csr_timeh
] = csr_output_value
.eq(minfo
.time_counter
[32:64])
515 c
[csr_instret
] = csr_output_value
.eq(minfo
.instret_counter
[0:32])
516 c
[csr_instreth
] = csr_output_value
.eq(minfo
.instret_counter
[32:64])
517 # mvendorid/march/mimpl/mhart
518 c
[csr_mvendorid
] = csr_output_value
.eq(minfo
.mvendorid
)
519 c
[csr_marchid
] = csr_output_value
.eq(minfo
.marchid
)
520 c
[csr_mimpid
] = csr_output_value
.eq(minfo
.mimpid
)
521 c
[csr_mhartid
] = csr_output_value
.eq(minfo
.mhartid
)
523 c
[csr_misa
] = csr_output_value
.eq(misa
.misa
)
526 csr_output_value
.eq(mstatus
.make()),
527 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
529 mstatus
.mpie
.eq(csr_written_value
[7]),
530 mstatus
.mie
.eq(csr_written_value
[3])
534 csr_output_value
.eq(mie
.make()),
535 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
537 mie
.meie
.eq(csr_written_value
[11]),
538 mie
.mtie
.eq(csr_written_value
[7]),
539 mie
.msie
.eq(csr_written_value
[3]),
542 c
[csr_mtvec
] = csr_output_value
.eq(mtvec
)
545 csr_output_value
.eq(m
.mscratch
),
546 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
549 m
.mscratch
.eq(csr_written_value
),
554 csr_output_value
.eq(m
.mepc
),
555 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
558 m
.mepc
.eq(csr_written_value
),
564 csr_output_value
.eq(m
.mcause
),
565 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
568 m
.mcause
.eq(csr_written_value
),
574 csr_output_value
.eq(mip
.make()),
575 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
579 return [Case(csr
.number
, c
),
581 self
.write_register(dc
.rd
, csr_output_value
)
586 csr_output_value = 0;
587 csr_output_value[11] = mip_meip;
588 csr_output_value[9] = mip_seip;
589 csr_output_value[8] = mip_ueip;
590 csr_output_value[7] = mip_mtip;
591 csr_output_value[5] = mip_stip;
592 csr_output_value[4] = mip_utip;
593 csr_output_value[3] = mip_msip;
594 csr_output_value[1] = mip_ssip;
595 csr_output_value[0] = mip_usip;
603 Module
.__init
__(self
)
604 self
.clk
= ClockSignal()
605 self
.reset
= ResetSignal()
606 self
.tty_write
= Signal()
607 self
.tty_write_data
= Signal(8)
608 self
.tty_write_busy
= Signal()
609 self
.switch_2
= Signal()
610 self
.switch_3
= Signal()
611 self
.led_1
= Signal()
612 self
.led_3
= Signal()
614 ram_size
= Constant(0x8000)
615 ram_start
= Constant(0x10000, 32)
616 reset_vector
= Signal(32)
619 reset_vector
.eq(ram_start
)
620 mtvec
.eq(ram_start
+ 0x40)
622 self
.regs
= Regs(self
.comb
, self
.sync
)
624 rf
= Instance("RegFile", name
="regfile",
625 i_ra_en
= self
.regs
.ra_en
,
626 i_rb_en
= self
.regs
.rb_en
,
627 i_w_en
= self
.regs
.w_en
,
628 o_read_a
= self
.regs
.rs1
,
629 o_read_b
= self
.regs
.rs2
,
630 i_writeval
= self
.regs
.wval
,
631 i_rs_a
= self
.regs
.rs_a
,
632 i_rs_b
= self
.regs
.rs_b
,
637 mi
= MemoryInterface()
639 mii
= Instance("cpu_memory_interface", name
="memory_instance",
640 p_ram_size
= ram_size
,
641 p_ram_start
= ram_start
,
644 i_fetch_address
= mi
.fetch_address
,
645 o_fetch_data
= mi
.fetch_data
,
646 o_fetch_valid
= mi
.fetch_valid
,
647 i_rw_address
= mi
.rw_address
,
648 i_rw_byte_mask
= mi
.rw_byte_mask
,
649 i_rw_read_not_write
= mi
.rw_read_not_write
,
650 i_rw_active
= mi
.rw_active
,
651 i_rw_data_in
= mi
.rw_data_in
,
652 o_rw_data_out
= mi
.rw_data_out
,
653 o_rw_address_valid
= mi
.rw_address_valid
,
654 o_rw_wait
= mi
.rw_wait
,
655 o_tty_write
= self
.tty_write
,
656 o_tty_write_data
= self
.tty_write_data
,
657 i_tty_write_busy
= self
.tty_write_busy
,
658 i_switch_2
= self
.switch_2
,
659 i_switch_3
= self
.switch_3
,
660 o_led_1
= self
.led_1
,
665 ft
= Fetch(self
.comb
, self
.sync
)
667 fs
= Instance("CPUFetchStage", name
="fetch_stage",
670 o_memory_interface_fetch_address
= mi
.fetch_address
,
671 i_memory_interface_fetch_data
= mi
.fetch_data
,
672 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
673 i_fetch_action
= ft
.action
,
674 i_target_pc
= ft
.target_pc
,
675 o_output_pc
= ft
.output_pc
,
676 o_output_instruction
= ft
.output_instruction
,
677 o_output_state
= ft
.output_state
,
678 i_reset_vector
= reset_vector
,
685 cd
= Instance("CPUDecoder", name
="decoder",
686 i_instruction
= ft
.output_instruction
,
687 o_funct7
= dc
.funct7
,
688 o_funct3
= dc
.funct3
,
692 o_immediate
= dc
.immediate
,
693 o_opcode
= dc
.opcode
,
694 o_decode_action
= dc
.act
698 self
.comb
+= self
.regs
.rs_a
.eq(dc
.rs1
)
699 self
.comb
+= self
.regs
.rs_b
.eq(dc
.rs2
)
701 load_store_address
= Signal(32)
702 load_store_address_low_2
= Signal(2)
704 self
.comb
+= load_store_address
.eq(dc
.immediate
+ self
.regs
.rs1
)
705 self
.comb
+= load_store_address_low_2
.eq(
706 dc
.immediate
[:2] + self
.regs
.rs1
[:2])
708 load_store_misaligned
= Signal()
710 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
711 load_store_address_low_2
)
714 # XXX rwaddr not 31:2 any more
715 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
717 unshifted_load_store_byte_mask
= Signal(4)
719 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
721 # XXX yuck. this will cause migen simulation to fail
722 # (however conversion to verilog works)
723 self
.comb
+= mi
.rw_byte_mask
.eq(
724 _Operator("<<", [unshifted_load_store_byte_mask
,
725 load_store_address_low_2
]))
728 b3
= Mux(load_store_address_low_2
[1],
729 Mux(load_store_address_low_2
[0], self
.regs
.rs2
[0:8],
730 self
.regs
.rs2
[8:16]),
731 Mux(load_store_address_low_2
[0], self
.regs
.rs2
[16:24],
732 self
.regs
.rs2
[24:32]))
733 b2
= Mux(load_store_address_low_2
[1], self
.regs
.rs2
[0:8],
734 self
.regs
.rs2
[16:24])
735 b1
= Mux(load_store_address_low_2
[0], self
.regs
.rs2
[0:8],
737 b0
= self
.regs
.rs2
[0:8]
739 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
742 unmasked_loaded_value
= Signal(32)
744 b0
= Mux(load_store_address_low_2
[1],
745 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
746 mi
.rw_data_out
[16:24]),
747 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
748 mi
.rw_data_out
[0:8]))
749 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
750 mi
.rw_data_out
[8:16])
751 b23
= mi
.rw_data_out
[16:32]
753 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
756 loaded_value
= Signal(32)
758 b0
= unmasked_loaded_value
[0:8]
759 b1
= Mux(dc
.funct3
[0:2] == 0,
760 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
761 unmasked_loaded_value
[8:16])
762 b2
= Mux(dc
.funct3
[1] == 0,
763 Replicate(~dc
.funct3
[2] &
764 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
765 unmasked_loaded_value
[7]),
767 unmasked_loaded_value
[16:32])
769 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
771 self
.comb
+= mi
.rw_active
.eq(~self
.reset
772 & (ft
.output_state
== FOS
.valid
)
773 & ~load_store_misaligned
774 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
776 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
781 alu_result
= Signal(32)
783 self
.comb
+= alu_a
.eq(self
.regs
.rs1
)
784 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
788 ali
= Instance("cpu_alu", name
="alu",
789 i_funct7
= dc
.funct7
,
790 i_funct3
= dc
.funct3
,
791 i_opcode
= dc
.opcode
,
794 o_result
= alu_result
798 lui_auipc_result
= Signal(32)
799 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
801 dc
.immediate
+ ft
.output_pc
))
803 self
.comb
+= ft
.target_pc
.eq(Cat(0,
804 Mux(dc
.opcode
!= OP
.jalr
,
806 self
.regs
.rs1
[1:32] + dc
.immediate
[1:32])))
808 misaligned_jump_target
= Signal()
809 self
.comb
+= misaligned_jump_target
.eq(ft
.target_pc
[1])
811 branch_arg_a
= Signal(32)
812 branch_arg_b
= Signal(32)
813 self
.comb
+= branch_arg_a
.eq(Cat( self
.regs
.rs1
[0:31],
814 self
.regs
.rs1
[31] ^ ~dc
.funct3
[1]))
815 self
.comb
+= branch_arg_b
.eq(Cat( self
.regs
.rs2
[0:31],
816 self
.regs
.rs2
[31] ^ ~dc
.funct3
[1]))
818 branch_taken
= Signal()
819 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
821 branch_arg_a
< branch_arg_b
,
822 branch_arg_a
== branch_arg_b
))
824 m
= M(self
.comb
, self
.sync
)
825 mstatus
= MStatus(self
.comb
, self
.sync
)
826 mie
= MIE(self
.comb
, self
.sync
)
827 misa
= Misa(self
.comb
, self
.sync
)
828 mip
= MIP(self
.comb
, self
.sync
)
831 csr
= CSR(self
.comb
, self
.sync
, dc
, self
.regs
.rs1
)
833 self
.comb
+= ft
.get_fetch_action(dc
.act
, load_store_misaligned
,
834 mi
.rw_wait
, mi
.rw_address_valid
,
835 branch_taken
, misaligned_jump_target
,
838 minfo
= MInfo(self
.comb
)
840 self
.sync
+= If(~self
.reset
,
841 self
.main_block(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
842 mstatus
, mie
, ft
, dc
,
843 load_store_misaligned
,
849 if __name__
== "__main__":
851 print(verilog
.convert(example
,
854 example
.tty_write_data
,
855 example
.tty_write_busy
,