3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 from migen
.fhdl
import verilog
31 from migen
.fhdl
.structure
import _Operator
33 from riscvdefs
import *
36 class MemoryInterface
:
37 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
38 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
39 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
40 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
41 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
42 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
43 rw_active
= Signal(name
="memory_interface_rw_active")
44 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
45 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
46 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
47 rw_wait
= Signal(name
="memory_interface_rw_wait")
51 funct7
= Signal(7, name
="decoder_funct7")
52 funct3
= Signal(3, name
="decoder_funct3")
53 rd
= Signal(5, name
="decoder_rd")
54 rs1
= Signal(5, name
="decoder_rs1")
55 rs2
= Signal(5, name
="decoder_rs2")
56 immediate
= Signal(32, name
="decoder_immediate")
57 opcode
= Signal(7, name
="decoder_opcode")
58 act
= Signal(decode_action
, name
="decoder_action")
65 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
66 return Case(funct3
[:2],
67 { F3
.sb
: ls
.eq(Constant(0)),
68 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
69 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
70 "default": ls
.eq(Constant(1))
73 def get_lsbm(self
, dc
):
74 return Cat(Constant(1),
75 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
76 Constant(1), Constant(0)),
78 Constant(0b11, 2), Constant(0, 2)))
81 self
.clk
= ClockSignal()
82 self
.reset
= ResetSignal()
83 self
.tty_write
= Signal()
84 self
.tty_write_data
= Signal(8)
85 self
.tty_write_busy
= Signal()
86 self
.switch_2
= Signal()
87 self
.switch_3
= Signal()
91 ram_size
= Constant(0x8000)
92 ram_start
= Constant(0x10000, 32)
93 reset_vector
= Signal(32)
96 reset_vector
.eq(ram_start
)
97 mtvec
.eq(ram_start
+ 0x40)
101 l
.append(Signal(32, name
="register%d" % i
))
104 mi
= MemoryInterface()
106 mii
= Instance("cpu_memory_interface", name
="memory_instance",
107 p_ram_size
= ram_size
,
108 p_ram_start
= ram_start
,
111 i_fetch_address
= mi
.fetch_address
,
112 o_fetch_data
= mi
.fetch_data
,
113 o_fetch_valid
= mi
.fetch_valid
,
114 i_rw_address
= mi
.rw_address
,
115 i_rw_byte_mask
= mi
.rw_byte_mask
,
116 i_rw_read_not_write
= mi
.rw_read_not_write
,
117 i_rw_active
= mi
.rw_active
,
118 i_rw_data_in
= mi
.rw_data_in
,
119 o_rw_data_out
= mi
.rw_data_out
,
120 o_rw_address_valid
= mi
.rw_address_valid
,
121 o_rw_wait
= mi
.rw_wait
,
122 o_tty_write
= self
.tty_write
,
123 o_tty_write_data
= self
.tty_write_data
,
124 i_tty_write_busy
= self
.tty_write_busy
,
125 i_switch_2
= self
.switch_2
,
126 i_switch_3
= self
.switch_3
,
127 o_led_1
= self
.led_1
,
132 fetch_act
= Signal(fetch_action
)
133 fetch_target_pc
= Signal(32)
134 fetch_output_pc
= Signal(32)
135 fetch_output_instruction
= Signal(32)
136 fetch_output_st
= Signal(fetch_output_state
)
138 fs
= Instance("CPUFetchStage", name
="fetch_stage",
141 o_memory_interface_fetch_address
= mi
.fetch_address
,
142 i_memory_interface_fetch_data
= mi
.fetch_data
,
143 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
144 i_fetch_action
= fetch_act
,
145 i_target_pc
= fetch_target_pc
,
146 o_output_pc
= fetch_output_pc
,
147 o_output_instruction
= fetch_output_instruction
,
148 o_output_state
= fetch_output_st
,
149 i_reset_vector
= reset_vector
,
156 cd
= Instance("CPUDecoder", name
="decoder",
157 i_instruction
= fetch_output_instruction
,
158 o_funct7
= dc
.funct7
,
159 o_funct3
= dc
.funct3
,
163 o_immediate
= dc
.immediate
,
164 o_opcode
= dc
.opcode
,
165 o_decode_action
= dc
.act
169 register_rs1
= Signal(32)
170 register_rs2
= Signal(32)
171 self
.comb
+= If(dc
.rs1
== 0,
174 register_rs1
.eq(registers
[dc
.rs1
-1]))
175 self
.comb
+= If(dc
.rs2
== 0,
178 register_rs2
.eq(registers
[dc
.rs2
-1]))
180 load_store_address
= Signal(32)
181 load_store_address_low_2
= Signal(2)
183 self
.comb
+= load_store_address
.eq(dc
.immediate
+ register_rs1
)
184 self
.comb
+= load_store_address_low_2
.eq(
185 dc
.immediate
[:2] + register_rs1
[:2])
187 load_store_misaligned
= Signal()
189 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
190 load_store_address_low_2
)
193 # XXX rwaddr not 31:2 any more
194 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
196 unshifted_load_store_byte_mask
= Signal(4)
198 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
200 # XXX yuck. this will cause migen simulation to fail
201 # (however conversion to verilog works)
202 self
.comb
+= mi
.rw_byte_mask
.eq(
203 _Operator("<<", [unshifted_load_store_byte_mask
,
204 load_store_address_low_2
]))
207 b3
= Mux(load_store_address_low_2
[1],
208 Mux(load_store_address_low_2
[0], register_rs2
[0:8],
210 Mux(load_store_address_low_2
[0], register_rs2
[16:24],
211 register_rs2
[24:32]))
212 b2
= Mux(load_store_address_low_2
[1], register_rs2
[0:8],
214 b1
= Mux(load_store_address_low_2
[0], register_rs2
[0:8],
216 b0
= register_rs2
[0:8]
218 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
221 unmasked_loaded_value
= Signal(32)
223 b0
= Mux(load_store_address_low_2
[1],
224 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
225 mi
.rw_data_out
[16:24]),
226 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
227 mi
.rw_data_out
[0:8]))
228 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
229 mi
.rw_data_out
[8:16])
230 b23
= mi
.rw_data_out
[16:32]
232 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
235 loaded_value
= Signal(32)
237 b0
= unmasked_loaded_value
[0:8]
238 b1
= Mux(dc
.funct3
[0:2] == 0,
239 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
240 unmasked_loaded_value
[8:16])
241 b2
= Mux(dc
.funct3
[1] == 0,
242 Replicate(~dc
.funct3
[2] &
243 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
244 unmasked_loaded_value
[7]),
246 unmasked_loaded_value
[16:32])
248 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
250 self
.comb
+= mi
.rw_active
.eq(~self
.reset
251 & (fetch_output_st
== fetch_output_state_valid
)
252 & ~load_store_misaligned
253 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
255 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
260 alu_result
= Signal(32)
262 self
.comb
+= alu_a
.eq(register_rs1
)
263 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
267 ali
= Instance("cpu_alu", name
="alu",
268 i_funct7
= dc
.funct7
,
269 i_funct3
= dc
.funct3
,
270 i_opcode
= dc
.opcode
,
273 o_result
= alu_result
277 lui_auipc_result
= Signal(32)
278 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
280 dc
.immediate
+ fetch_output_pc
))
282 if __name__
== "__main__":
284 print(verilog
.convert(example
,
287 example
.tty_write_data
,
288 example
.tty_write_busy
,
297 wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
299 assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
300 assign fetch_target_pc[0] = 0;
302 wire misaligned_jump_target = fetch_target_pc[1];
304 wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
305 wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
307 wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
309 reg [31:0] mcause = 0;
310 reg [31:0] mepc = 32'hXXXXXXXX;
311 reg [31:0] mscratch = 32'hXXXXXXXX;
313 reg mstatus_mpie = 1'bX;
315 parameter mstatus_mprv = 0;
316 parameter mstatus_tsr = 0;
317 parameter mstatus_tw = 0;
318 parameter mstatus_tvm = 0;
319 parameter mstatus_mxr = 0;
320 parameter mstatus_sum = 0;
321 parameter mstatus_xs = 0;
322 parameter mstatus_fs = 0;
323 parameter mstatus_mpp = 2'b11;
324 parameter mstatus_spp = 0;
325 parameter mstatus_spie = 0;
326 parameter mstatus_upie = 0;
327 parameter mstatus_sie = 0;
328 parameter mstatus_uie = 0;
333 parameter mie_seie = 0;
334 parameter mie_ueie = 0;
335 parameter mie_stie = 0;
336 parameter mie_utie = 0;
337 parameter mie_ssie = 0;
338 parameter mie_usie = 0;
340 task reset_to_initial;
344 mscratch = 32'hXXXXXXXX;
350 registers['h01] <= 32'hXXXXXXXX;
351 registers['h02] <= 32'hXXXXXXXX;
352 registers['h03] <= 32'hXXXXXXXX;
353 registers['h04] <= 32'hXXXXXXXX;
354 registers['h05] <= 32'hXXXXXXXX;
355 registers['h06] <= 32'hXXXXXXXX;
356 registers['h07] <= 32'hXXXXXXXX;
357 registers['h08] <= 32'hXXXXXXXX;
358 registers['h09] <= 32'hXXXXXXXX;
359 registers['h0A] <= 32'hXXXXXXXX;
360 registers['h0B] <= 32'hXXXXXXXX;
361 registers['h0C] <= 32'hXXXXXXXX;
362 registers['h0D] <= 32'hXXXXXXXX;
363 registers['h0E] <= 32'hXXXXXXXX;
364 registers['h0F] <= 32'hXXXXXXXX;
365 registers['h10] <= 32'hXXXXXXXX;
366 registers['h11] <= 32'hXXXXXXXX;
367 registers['h12] <= 32'hXXXXXXXX;
368 registers['h13] <= 32'hXXXXXXXX;
369 registers['h14] <= 32'hXXXXXXXX;
370 registers['h15] <= 32'hXXXXXXXX;
371 registers['h16] <= 32'hXXXXXXXX;
372 registers['h17] <= 32'hXXXXXXXX;
373 registers['h18] <= 32'hXXXXXXXX;
374 registers['h19] <= 32'hXXXXXXXX;
375 registers['h1A] <= 32'hXXXXXXXX;
376 registers['h1B] <= 32'hXXXXXXXX;
377 registers['h1C] <= 32'hXXXXXXXX;
378 registers['h1D] <= 32'hXXXXXXXX;
379 registers['h1E] <= 32'hXXXXXXXX;
380 registers['h1F] <= 32'hXXXXXXXX;
384 task write_register(input [4:0] register_number, input [31:0] value);
386 if(register_number != 0)
387 registers[register_number] <= value;
391 function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
394 `funct3_csrrw, `funct3_csrrwi:
395 evaluate_csr_funct3_operation = written_value;
396 `funct3_csrrs, `funct3_csrrsi:
397 evaluate_csr_funct3_operation = written_value | previous_value;
398 `funct3_csrrc, `funct3_csrrci:
399 evaluate_csr_funct3_operation = ~written_value & previous_value;
401 evaluate_csr_funct3_operation = 32'hXXXXXXXX;
406 parameter misa_a = 1'b0;
407 parameter misa_b = 1'b0;
408 parameter misa_c = 1'b0;
409 parameter misa_d = 1'b0;
410 parameter misa_e = 1'b0;
411 parameter misa_f = 1'b0;
412 parameter misa_g = 1'b0;
413 parameter misa_h = 1'b0;
414 parameter misa_i = 1'b1;
415 parameter misa_j = 1'b0;
416 parameter misa_k = 1'b0;
417 parameter misa_l = 1'b0;
418 parameter misa_m = 1'b0;
419 parameter misa_n = 1'b0;
420 parameter misa_o = 1'b0;
421 parameter misa_p = 1'b0;
422 parameter misa_q = 1'b0;
423 parameter misa_r = 1'b0;
424 parameter misa_s = 1'b0;
425 parameter misa_t = 1'b0;
426 parameter misa_u = 1'b0;
427 parameter misa_v = 1'b0;
428 parameter misa_w = 1'b0;
429 parameter misa_x = 1'b0;
430 parameter misa_y = 1'b0;
431 parameter misa_z = 1'b0;
462 parameter mvendorid = 32'b0;
463 parameter marchid = 32'b0;
464 parameter mimpid = 32'b0;
465 parameter mhartid = 32'b0;
467 function [31:0] make_mstatus(input mstatus_tsr,
473 input [1:0] mstatus_xs,
474 input [1:0] mstatus_fs,
475 input [1:0] mstatus_mpp,
484 make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
508 wire mip_meip = 0; // TODO: implement external interrupts
509 parameter mip_seip = 0;
510 parameter mip_ueip = 0;
511 wire mip_mtip = 0; // TODO: implement timer interrupts
512 parameter mip_stip = 0;
513 parameter mip_utip = 0;
514 parameter mip_msip = 0;
515 parameter mip_ssip = 0;
516 parameter mip_usip = 0;
518 wire csr_op_is_valid;
520 function `fetch_action get_fetch_action(
521 input `fetch_output_state fetch_output_state,
522 input `decode_action decode_action,
523 input load_store_misaligned,
524 input memory_interface_rw_address_valid,
525 input memory_interface_rw_wait,
527 input misaligned_jump_target,
528 input csr_op_is_valid
531 case(fetch_output_state)
532 `fetch_output_state_empty:
533 get_fetch_action = `fetch_action_default;
534 `fetch_output_state_trap:
535 get_fetch_action = `fetch_action_ack_trap;
536 `fetch_output_state_valid: begin
537 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
538 get_fetch_action = `fetch_action_error_trap;
540 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
541 get_fetch_action = `fetch_action_noerror_trap;
543 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
544 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
545 get_fetch_action = `fetch_action_error_trap;
547 else if(memory_interface_rw_wait) begin
548 get_fetch_action = `fetch_action_wait;
551 get_fetch_action = `fetch_action_default;
554 else if((decode_action & `decode_action_fence_i) != 0) begin
555 get_fetch_action = `fetch_action_fence;
557 else if((decode_action & `decode_action_branch) != 0) begin
558 if(branch_taken) begin
559 if(misaligned_jump_target) begin
560 get_fetch_action = `fetch_action_error_trap;
563 get_fetch_action = `fetch_action_jump;
568 get_fetch_action = `fetch_action_default;
571 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
572 if(misaligned_jump_target) begin
573 get_fetch_action = `fetch_action_error_trap;
576 get_fetch_action = `fetch_action_jump;
579 else if((decode_action & `decode_action_csr) != 0) begin
581 get_fetch_action = `fetch_action_default;
583 get_fetch_action = `fetch_action_error_trap;
586 get_fetch_action = `fetch_action_default;
590 get_fetch_action = 32'hXXXXXXXX;
595 assign fetch_action = get_fetch_action(
598 load_store_misaligned,
599 memory_interface_rw_address_valid,
600 memory_interface_rw_wait,
602 misaligned_jump_target,
608 mstatus_mpie = mstatus_mie;
610 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
611 if(fetch_action == `fetch_action_ack_trap) begin
612 mcause = `cause_instruction_access_fault;
614 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
615 mcause = `cause_illegal_instruction;
617 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
618 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
620 else if((decode_action & `decode_action_load) != 0) begin
621 if(load_store_misaligned)
622 mcause = `cause_load_address_misaligned;
624 mcause = `cause_load_access_fault;
626 else if((decode_action & `decode_action_store) != 0) begin
627 if(load_store_misaligned)
628 mcause = `cause_store_amo_address_misaligned;
630 mcause = `cause_store_amo_access_fault;
632 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
633 mcause = `cause_instruction_address_misaligned;
636 mcause = `cause_illegal_instruction;
641 wire [11:0] csr_number = decoder_immediate;
642 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
643 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
644 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
646 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
677 get_csr_op_is_valid = 0;
688 get_csr_op_is_valid = ~csr_writes;
697 get_csr_op_is_valid = 1;
704 // TODO: CSRs not implemented yet
705 get_csr_op_is_valid = 0;
710 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
712 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
713 wire [63:0] time_counter = 0; // TODO: implement time_counter
714 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
716 always @(posedge clk) begin:main_block
721 case(fetch_output_state)
722 `fetch_output_state_empty: begin
724 `fetch_output_state_trap: begin
727 `fetch_output_state_valid: begin:valid
728 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
731 else if((decode_action & `decode_action_load) != 0) begin
732 if(~memory_interface_rw_wait)
733 write_register(decoder_rd, loaded_value);
735 else if((decode_action & `decode_action_op_op_imm) != 0) begin
736 write_register(decoder_rd, alu_result);
738 else if((decode_action & `decode_action_lui_auipc) != 0) begin
739 write_register(decoder_rd, lui_auipc_result);
741 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
742 write_register(decoder_rd, fetch_output_pc + 4);
744 else if((decode_action & `decode_action_csr) != 0) begin:csr
745 reg [31:0] csr_output_value;
746 reg [31:0] csr_written_value;
747 csr_output_value = 32'hXXXXXXXX;
748 csr_written_value = 32'hXXXXXXXX;
751 csr_output_value = cycle_counter[31:0];
754 csr_output_value = time_counter[31:0];
757 csr_output_value = instret_counter[31:0];
760 csr_output_value = cycle_counter[63:32];
763 csr_output_value = time_counter[63:32];
766 csr_output_value = instret_counter[63:32];
768 `csr_mvendorid: begin
769 csr_output_value = mvendorid;
772 csr_output_value = marchid;
775 csr_output_value = mimpid;
778 csr_output_value = mhartid;
781 csr_output_value = misa;
784 csr_output_value = make_mstatus(mstatus_tsr,
800 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
802 mstatus_mpie = csr_written_value[7];
803 mstatus_mie = csr_written_value[3];
807 csr_output_value = 0;
808 csr_output_value[11] = mie_meie;
809 csr_output_value[9] = mie_seie;
810 csr_output_value[8] = mie_ueie;
811 csr_output_value[7] = mie_mtie;
812 csr_output_value[5] = mie_stie;
813 csr_output_value[4] = mie_utie;
814 csr_output_value[3] = mie_msie;
815 csr_output_value[1] = mie_ssie;
816 csr_output_value[0] = mie_usie;
817 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
819 mie_meie = csr_written_value[11];
820 mie_mtie = csr_written_value[7];
821 mie_msie = csr_written_value[3];
825 csr_output_value = mtvec;
828 csr_output_value = mscratch;
829 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
831 mscratch = csr_written_value;
834 csr_output_value = mepc;
835 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
837 mepc = csr_written_value;
840 csr_output_value = mcause;
841 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
843 mcause = csr_written_value;
846 csr_output_value = 0;
847 csr_output_value[11] = mip_meip;
848 csr_output_value[9] = mip_seip;
849 csr_output_value[8] = mip_ueip;
850 csr_output_value[7] = mip_mtip;
851 csr_output_value[5] = mip_stip;
852 csr_output_value[4] = mip_utip;
853 csr_output_value[3] = mip_msip;
854 csr_output_value[1] = mip_ssip;
855 csr_output_value[0] = mip_usip;
859 write_register(decoder_rd, csr_output_value);
861 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin