2 * Copyright 2018 Jacob Lifshay
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in all
12 * copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 output [7:0] tty_write_data,
39 parameter ram_size = 'h8000;
40 parameter ram_start = 32'h1_0000;
41 parameter reset_vector = ram_start;
42 parameter mtvec = ram_start + 'h40;
44 reg [31:0] registers[31:1];
46 wire [31:2] memory_interface_fetch_address;
47 wire [31:0] memory_interface_fetch_data;
48 wire memory_interface_fetch_valid;
49 wire [31:2] memory_interface_rw_address;
50 wire [3:0] memory_interface_rw_byte_mask;
51 wire memory_interface_rw_read_not_write;
52 wire memory_interface_rw_active;
53 wire [31:0] memory_interface_rw_data_in;
54 wire [31:0] memory_interface_rw_data_out;
55 wire memory_interface_rw_address_valid;
56 wire memory_interface_rw_wait;
58 cpu_memory_interface #(
64 .fetch_address(memory_interface_fetch_address),
65 .fetch_data(memory_interface_fetch_data),
66 .fetch_valid(memory_interface_fetch_valid),
67 .rw_address(memory_interface_rw_address),
68 .rw_byte_mask(memory_interface_rw_byte_mask),
69 .rw_read_not_write(memory_interface_rw_read_not_write),
70 .rw_active(memory_interface_rw_active),
71 .rw_data_in(memory_interface_rw_data_in),
72 .rw_data_out(memory_interface_rw_data_out),
73 .rw_address_valid(memory_interface_rw_address_valid),
74 .rw_wait(memory_interface_rw_wait),
75 .tty_write(tty_write),
76 .tty_write_data(tty_write_data),
77 .tty_write_busy(tty_write_busy),
84 wire `fetch_action fetch_action;
85 wire [31:0] fetch_target_pc;
86 wire [31:0] fetch_output_pc;
87 wire [31:0] fetch_output_instruction;
88 wire `fetch_output_state fetch_output_state;
91 .reset_vector(reset_vector),
96 .memory_interface_fetch_address(memory_interface_fetch_address),
97 .memory_interface_fetch_data(memory_interface_fetch_data),
98 .memory_interface_fetch_valid(memory_interface_fetch_valid),
99 .fetch_action(fetch_action),
100 .target_pc(fetch_target_pc),
101 .output_pc(fetch_output_pc),
102 .output_instruction(fetch_output_instruction),
103 .output_state(fetch_output_state)
106 wire [6:0] decoder_funct7;
107 wire [2:0] decoder_funct3;
108 wire [4:0] decoder_rd;
109 wire [4:0] decoder_rs1;
110 wire [4:0] decoder_rs2;
111 wire [31:0] decoder_immediate;
112 wire [6:0] decoder_opcode;
113 wire `decode_action decode_action;
116 .instruction(fetch_output_instruction),
117 .funct7(decoder_funct7),
118 .funct3(decoder_funct3),
122 .immediate(decoder_immediate),
123 .opcode(decoder_opcode),
124 .decode_action(decode_action));
126 wire [31:0] register_rs1 = (decoder_rs1 == 0) ? 0 : registers[decoder_rs1];
127 wire [31:0] register_rs2 = (decoder_rs2 == 0) ? 0 : registers[decoder_rs2];
129 wire [31:0] load_store_address = decoder_immediate + register_rs1;
131 wire [1:0] load_store_address_low_2 = decoder_immediate[1:0] + register_rs1[1:0];
133 function get_load_store_misaligned(
135 input [1:0] load_store_address_low_2
140 get_load_store_misaligned = 0;
142 get_load_store_misaligned = load_store_address_low_2[0] != 0;
144 get_load_store_misaligned = load_store_address_low_2[1:0] != 0;
146 get_load_store_misaligned = 1'bX;
151 wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2);
153 assign memory_interface_rw_address = load_store_address[31:2];
155 wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
157 assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
159 assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
160 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
161 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
162 assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
163 assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
164 assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
166 wire [31:0] unmasked_loaded_value;
168 assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
169 ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
170 : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
171 assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
172 assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
174 wire [31:0] loaded_value;
176 assign loaded_value[7:0] = unmasked_loaded_value[7:0];
177 assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
178 assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
180 assign memory_interface_rw_active = ~reset
181 & (fetch_output_state == `fetch_output_state_valid)
182 & ~load_store_misaligned
183 & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
185 assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
187 wire [31:0] alu_a = register_rs1;
188 wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
189 wire [31:0] alu_result;
192 .funct7(decoder_funct7),
193 .funct3(decoder_funct3),
194 .opcode(decoder_opcode),
200 wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
202 assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
203 assign fetch_target_pc[0] = 0;
205 wire misaligned_jump_target = fetch_target_pc[1];
207 wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
208 wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
210 wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
212 reg [31:0] mcause = 0;
213 reg [31:0] mepc = 32'hXXXXXXXX;
214 reg [31:0] mscratch = 32'hXXXXXXXX;
216 reg mstatus_mpie = 1'bX;
218 parameter mstatus_mprv = 0;
219 parameter mstatus_tsr = 0;
220 parameter mstatus_tw = 0;
221 parameter mstatus_tvm = 0;
222 parameter mstatus_mxr = 0;
223 parameter mstatus_sum = 0;
224 parameter mstatus_xs = 0;
225 parameter mstatus_fs = 0;
226 parameter mstatus_mpp = 2'b11;
227 parameter mstatus_spp = 0;
228 parameter mstatus_spie = 0;
229 parameter mstatus_upie = 0;
230 parameter mstatus_sie = 0;
231 parameter mstatus_uie = 0;
236 parameter mie_seie = 0;
237 parameter mie_ueie = 0;
238 parameter mie_stie = 0;
239 parameter mie_utie = 0;
240 parameter mie_ssie = 0;
241 parameter mie_usie = 0;
243 task reset_to_initial;
247 mscratch = 32'hXXXXXXXX;
253 registers['h01] <= 32'hXXXXXXXX;
254 registers['h02] <= 32'hXXXXXXXX;
255 registers['h03] <= 32'hXXXXXXXX;
256 registers['h04] <= 32'hXXXXXXXX;
257 registers['h05] <= 32'hXXXXXXXX;
258 registers['h06] <= 32'hXXXXXXXX;
259 registers['h07] <= 32'hXXXXXXXX;
260 registers['h08] <= 32'hXXXXXXXX;
261 registers['h09] <= 32'hXXXXXXXX;
262 registers['h0A] <= 32'hXXXXXXXX;
263 registers['h0B] <= 32'hXXXXXXXX;
264 registers['h0C] <= 32'hXXXXXXXX;
265 registers['h0D] <= 32'hXXXXXXXX;
266 registers['h0E] <= 32'hXXXXXXXX;
267 registers['h0F] <= 32'hXXXXXXXX;
268 registers['h10] <= 32'hXXXXXXXX;
269 registers['h11] <= 32'hXXXXXXXX;
270 registers['h12] <= 32'hXXXXXXXX;
271 registers['h13] <= 32'hXXXXXXXX;
272 registers['h14] <= 32'hXXXXXXXX;
273 registers['h15] <= 32'hXXXXXXXX;
274 registers['h16] <= 32'hXXXXXXXX;
275 registers['h17] <= 32'hXXXXXXXX;
276 registers['h18] <= 32'hXXXXXXXX;
277 registers['h19] <= 32'hXXXXXXXX;
278 registers['h1A] <= 32'hXXXXXXXX;
279 registers['h1B] <= 32'hXXXXXXXX;
280 registers['h1C] <= 32'hXXXXXXXX;
281 registers['h1D] <= 32'hXXXXXXXX;
282 registers['h1E] <= 32'hXXXXXXXX;
283 registers['h1F] <= 32'hXXXXXXXX;
287 task write_register(input [4:0] register_number, input [31:0] value);
289 if(register_number != 0)
290 registers[register_number] <= value;
294 function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
297 `funct3_csrrw, `funct3_csrrwi:
298 evaluate_csr_funct3_operation = written_value;
299 `funct3_csrrs, `funct3_csrrsi:
300 evaluate_csr_funct3_operation = written_value | previous_value;
301 `funct3_csrrc, `funct3_csrrci:
302 evaluate_csr_funct3_operation = ~written_value & previous_value;
304 evaluate_csr_funct3_operation = 32'hXXXXXXXX;
309 parameter misa_a = 1'b0;
310 parameter misa_b = 1'b0;
311 parameter misa_c = 1'b0;
312 parameter misa_d = 1'b0;
313 parameter misa_e = 1'b0;
314 parameter misa_f = 1'b0;
315 parameter misa_g = 1'b0;
316 parameter misa_h = 1'b0;
317 parameter misa_i = 1'b1;
318 parameter misa_j = 1'b0;
319 parameter misa_k = 1'b0;
320 parameter misa_l = 1'b0;
321 parameter misa_m = 1'b0;
322 parameter misa_n = 1'b0;
323 parameter misa_o = 1'b0;
324 parameter misa_p = 1'b0;
325 parameter misa_q = 1'b0;
326 parameter misa_r = 1'b0;
327 parameter misa_s = 1'b0;
328 parameter misa_t = 1'b0;
329 parameter misa_u = 1'b0;
330 parameter misa_v = 1'b0;
331 parameter misa_w = 1'b0;
332 parameter misa_x = 1'b0;
333 parameter misa_y = 1'b0;
334 parameter misa_z = 1'b0;
365 parameter mvendorid = 32'b0;
366 parameter marchid = 32'b0;
367 parameter mimpid = 32'b0;
368 parameter mhartid = 32'b0;
370 function [31:0] make_mstatus(input mstatus_tsr,
376 input [1:0] mstatus_xs,
377 input [1:0] mstatus_fs,
378 input [1:0] mstatus_mpp,
387 make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
411 wire mip_meip = 0; // TODO: implement external interrupts
412 parameter mip_seip = 0;
413 parameter mip_ueip = 0;
414 wire mip_mtip = 0; // TODO: implement timer interrupts
415 parameter mip_stip = 0;
416 parameter mip_utip = 0;
417 parameter mip_msip = 0;
418 parameter mip_ssip = 0;
419 parameter mip_usip = 0;
421 wire csr_op_is_valid;
423 function `fetch_action get_fetch_action(
424 input `fetch_output_state fetch_output_state,
425 input `decode_action decode_action,
426 input load_store_misaligned,
427 input memory_interface_rw_address_valid,
428 input memory_interface_rw_wait,
430 input misaligned_jump_target,
431 input csr_op_is_valid
434 case(fetch_output_state)
435 `fetch_output_state_empty:
436 get_fetch_action = `fetch_action_default;
437 `fetch_output_state_trap:
438 get_fetch_action = `fetch_action_ack_trap;
439 `fetch_output_state_valid: begin
440 if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
441 get_fetch_action = `fetch_action_error_trap;
443 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
444 get_fetch_action = `fetch_action_noerror_trap;
446 else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
447 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
448 get_fetch_action = `fetch_action_error_trap;
450 else if(memory_interface_rw_wait) begin
451 get_fetch_action = `fetch_action_wait;
454 get_fetch_action = `fetch_action_default;
457 else if((decode_action & `decode_action_fence_i) != 0) begin
458 get_fetch_action = `fetch_action_fence;
460 else if((decode_action & `decode_action_branch) != 0) begin
461 if(branch_taken) begin
462 if(misaligned_jump_target) begin
463 get_fetch_action = `fetch_action_error_trap;
466 get_fetch_action = `fetch_action_jump;
471 get_fetch_action = `fetch_action_default;
474 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
475 if(misaligned_jump_target) begin
476 get_fetch_action = `fetch_action_error_trap;
479 get_fetch_action = `fetch_action_jump;
482 else if((decode_action & `decode_action_csr) != 0) begin
484 get_fetch_action = `fetch_action_default;
486 get_fetch_action = `fetch_action_error_trap;
489 get_fetch_action = `fetch_action_default;
493 get_fetch_action = 32'hXXXXXXXX;
498 assign fetch_action = get_fetch_action(
501 load_store_misaligned,
502 memory_interface_rw_address_valid,
503 memory_interface_rw_wait,
505 misaligned_jump_target,
511 mstatus_mpie = mstatus_mie;
513 mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
514 if(fetch_action == `fetch_action_ack_trap) begin
515 mcause = `cause_instruction_access_fault;
517 else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
518 mcause = `cause_illegal_instruction;
520 else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
521 mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
523 else if((decode_action & `decode_action_load) != 0) begin
524 if(load_store_misaligned)
525 mcause = `cause_load_address_misaligned;
527 mcause = `cause_load_access_fault;
529 else if((decode_action & `decode_action_store) != 0) begin
530 if(load_store_misaligned)
531 mcause = `cause_store_amo_address_misaligned;
533 mcause = `cause_store_amo_access_fault;
535 else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
536 mcause = `cause_instruction_address_misaligned;
539 mcause = `cause_illegal_instruction;
544 wire [11:0] csr_number = decoder_immediate;
545 wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
546 wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
547 wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
549 function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
580 get_csr_op_is_valid = 0;
591 get_csr_op_is_valid = ~csr_writes;
600 get_csr_op_is_valid = 1;
607 // TODO: CSRs not implemented yet
608 get_csr_op_is_valid = 0;
613 assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
615 wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
616 wire [63:0] time_counter = 0; // TODO: implement time_counter
617 wire [63:0] instret_counter = 0; // TODO: implement instret_counter
619 always @(posedge clk) begin:main_block
624 case(fetch_output_state)
625 `fetch_output_state_empty: begin
627 `fetch_output_state_trap: begin
630 `fetch_output_state_valid: begin:valid
631 if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
634 else if((decode_action & `decode_action_load) != 0) begin
635 if(~memory_interface_rw_wait)
636 write_register(decoder_rd, loaded_value);
638 else if((decode_action & `decode_action_op_op_imm) != 0) begin
639 write_register(decoder_rd, alu_result);
641 else if((decode_action & `decode_action_lui_auipc) != 0) begin
642 write_register(decoder_rd, lui_auipc_result);
644 else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
645 write_register(decoder_rd, fetch_output_pc + 4);
647 else if((decode_action & `decode_action_csr) != 0) begin:csr
648 reg [31:0] csr_output_value;
649 reg [31:0] csr_written_value;
650 csr_output_value = 32'hXXXXXXXX;
651 csr_written_value = 32'hXXXXXXXX;
654 csr_output_value = cycle_counter[31:0];
657 csr_output_value = time_counter[31:0];
660 csr_output_value = instret_counter[31:0];
663 csr_output_value = cycle_counter[63:32];
666 csr_output_value = time_counter[63:32];
669 csr_output_value = instret_counter[63:32];
671 `csr_mvendorid: begin
672 csr_output_value = mvendorid;
675 csr_output_value = marchid;
678 csr_output_value = mimpid;
681 csr_output_value = mhartid;
684 csr_output_value = misa;
687 csr_output_value = make_mstatus(mstatus_tsr,
703 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
705 mstatus_mpie = csr_written_value[7];
706 mstatus_mie = csr_written_value[3];
710 csr_output_value = 0;
711 csr_output_value[11] = mie_meie;
712 csr_output_value[9] = mie_seie;
713 csr_output_value[8] = mie_ueie;
714 csr_output_value[7] = mie_mtie;
715 csr_output_value[5] = mie_stie;
716 csr_output_value[4] = mie_utie;
717 csr_output_value[3] = mie_msie;
718 csr_output_value[1] = mie_ssie;
719 csr_output_value[0] = mie_usie;
720 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
722 mie_meie = csr_written_value[11];
723 mie_mtie = csr_written_value[7];
724 mie_msie = csr_written_value[3];
728 csr_output_value = mtvec;
731 csr_output_value = mscratch;
732 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
734 mscratch = csr_written_value;
737 csr_output_value = mepc;
738 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
740 mepc = csr_written_value;
743 csr_output_value = mcause;
744 csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
746 mcause = csr_written_value;
749 csr_output_value = 0;
750 csr_output_value[11] = mip_meip;
751 csr_output_value[9] = mip_seip;
752 csr_output_value[8] = mip_ueip;
753 csr_output_value[7] = mip_mtip;
754 csr_output_value[5] = mip_stip;
755 csr_output_value[4] = mip_utip;
756 csr_output_value[3] = mip_msip;
757 csr_output_value[1] = mip_ssip;
758 csr_output_value[0] = mip_usip;
762 write_register(decoder_rd, csr_output_value);
764 else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin