3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 from migen
.fhdl
import verilog
29 from riscvdefs
import *
32 reset_vector
= 32'hXXXXXXXX;
35 class CPUFetchStage(Module
):
37 self
.clk
= ClockSignal()
38 self
.reset
= ResetSignal()
39 #output [31:2] memory_interface_fetch_address,
40 self
.memory_interface_fetch_address
= Signal(32)[2:]
41 #input [31:0] memory_interface_fetch_data,
42 self
.memory_interface_fetch_data
= Signal(32)
43 self
.memory_interface_fetch_valid
= Signal()
44 self
.fetch_action
= Signal(fetch_action
)
45 self
.target_pc
= Signal(32)
46 self
.output_pc
= Signal(32, reset
=reset_vector
)
47 self
.output_instruction
= Signal(32)
48 self
.output_state
= Signal(fetch_output_state
,
49 reset
=fetch_output_state_empty
)
52 self
.cd_sys
.clk
.eq(self
.clk
),
53 self
.cd_sys
.rst
.eq(self
.reset
)
56 fetch_pc
= Signal(32, reset
=reset_vector
)
58 self
.sync
+= If(fetch_action
!= fetch_action_wait
,
59 output_pc
.eq(fetch_pc
))
61 memory_interface_fetch_address
= fetch_pc
[2:]
63 initial output_pc
<= reset_vector
;
64 initial output_state
<= `fetch_output_state_empty
;
66 delayed_instruction
= Signal(32, reset
=0)
67 delayed_instruction_valid
= Signal(reset
=0)
69 self
.sync
+= delayed_instruction
.eq(output_instruction
)
70 self
.sync
+= output_state
.eq(fetch_output_state_empty
)
72 self
.comb
+= If(delayed_instruction_valid
,
73 output_instruction
.eq(delayed_instruction
)
75 output_instruction
.eq(memory_interface_fetch_data
)
78 self
.sync
+= delayed_instruction_valid
.eq(fetch_action
==
82 fetch_action_ack_trap
:
83 If(memory_interface_fetch_valid
,
84 [fetch_pc
.eq(fetch_pc
+ 4),
85 output_state
.eq(fetch_output_state_valid
)]
88 output_state
.eq(fetch_output_state_trap
)]
91 [ fetch_pc
.eq(output_pc
+ 4),
92 output_state
.eq(fetch_output_state_empty
)
95 [ fetch_pc
.eq(target_pc
),
96 output_state
.eq(fetch_output_state_empty
)
98 fetch_action_error_trap
,
100 output_state
.eq(fetch_output_state_empty
)
103 [fetch_pc
.eq(fetch_pc
),
104 output_state
.eq(fetch_output_state_valid
)
107 fc
[fetch_action_default
] = fc
[fetch_action_ack_trap
]
108 fc
[fetch_action_noerror_trap
] = fc
[fetch_action_error_trap
]
109 self
.sync
+= Case(fetch_action
, fc
).makedefault(fetch_action_default
)