3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 from migen
.fhdl
import verilog
29 #from riscvdefs import *
33 class CPUFetchStage(Module
):
35 self
.clk
= ClockSignal()
36 self
.reset
= ResetSignal()
37 #output [31:2] memory_interface_fetch_address,
38 self
.memory_interface_fetch_address
= Signal(32)
39 #input [31:0] memory_interface_fetch_data,
40 self
.memory_interface_fetch_data
= Signal(32)
41 self
.memory_interface_fetch_valid
= Signal()
42 self
.fetch_action
= Signal(fetch_action
)
43 self
.target_pc
= Signal(32)
44 self
.output_pc
= Signal(32, reset
=reset_vector
)
45 self
.output_instruction
= Signal(32)
46 self
.output_state
= Signal(fetch_output_state
,
47 reset
=fetch_output_state_empty
)
48 self
.reset_vector
= Signal(32) #32'hXXXXXXXX; - parameter
49 self
.mtvec
= Signal(32) # 32'hXXXXXXXX; - parameter
52 # self.cd_sys.clk.eq(self.clk),
53 # self.cd_sys.rst.eq(self.reset)
56 fetch_pc
= Signal(32, reset
=reset_vector
)
58 self
.sync
+= If(self
.fetch_action
!= fetch_action_wait
,
59 self
.output_pc
.eq(fetch_pc
))
61 self
.comb
+= self
.memory_interface_fetch_address
.eq(fetch_pc
[2:])
63 #initial output_pc <= reset_vector;
64 #initial output_state <= `fetch_output_state_empty;
66 delayed_instruction
= Signal(32, reset
=0)
67 delayed_instruction_valid
= Signal(reset
=0)
69 self
.sync
+= delayed_instruction
.eq(self
.output_instruction
)
71 self
.comb
+= If(delayed_instruction_valid
,
72 self
.output_instruction
.eq(delayed_instruction
)
74 self
.output_instruction
.eq(self
.memory_interface_fetch_data
)
77 self
.sync
+= delayed_instruction_valid
.eq(self
.fetch_action
==
81 fetch_action_ack_trap
:
82 If(self
.memory_interface_fetch_valid
,
83 [fetch_pc
.eq(fetch_pc
+ 4),
84 self
.output_state
.eq(fetch_output_state_valid
)]
87 self
.output_state
.eq(fetch_output_state_trap
)]
90 [ fetch_pc
.eq(self
.output_pc
+ 4),
91 self
.output_state
.eq(fetch_output_state_empty
)
94 [ fetch_pc
.eq(self
.target_pc
),
95 self
.output_state
.eq(fetch_output_state_empty
)
97 fetch_action_error_trap
:
99 self
.output_state
.eq(fetch_output_state_empty
)
102 [fetch_pc
.eq(fetch_pc
),
103 self
.output_state
.eq(fetch_output_state_valid
)
106 fc
[fetch_action_default
] = fc
[fetch_action_ack_trap
]
107 fc
[fetch_action_noerror_trap
] = fc
[fetch_action_error_trap
]
108 self
.sync
+= Case(self
.fetch_action
,
109 fc
).makedefault(fetch_action_default
)
111 if __name__
== "__main__":
112 example
= CPUFetchStage()
113 #memory_interface_fetch_address = Signal(32)
114 print(verilog
.convert(example
,
117 example
.memory_interface_fetch_address
,
118 example
.memory_interface_fetch_data
,
119 example
.memory_interface_fetch_valid
,
120 example
.fetch_action
,
123 example
.output_instruction
,
125 example
.reset_vector
,