3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
40 # TODO: implement ext interrupts
41 self
.meip
= Signal(name
="mip_meip", reset
=0)
42 self
.seip
= Signal(name
="mip_seip", reset
=0)
43 self
.ueip
= Signal(name
="mip_uiep", reset
=0)
44 # TODO: implement timer interrupts
45 self
.mtip
= Signal(name
="mip_mtip", reset
=0)
46 self
.stip
= Signal(name
="mip_stip", reset
=0)
47 self
.msip
= Signal(name
="mip_stip", reset
=0)
48 self
.utip
= Signal(name
="mip_utip", reset
=0)
49 self
.ssip
= Signal(name
="mip_ssip", reset
=0)
50 self
.usip
= Signal(name
="mip_usip", reset
=0)
53 self
.comb
+= self
.mip
.eq(self
.make())
56 return Cat( self
.usip
, self
.ssip
, 0, self
.msip
,
57 self
.utip
, self
.stip
, 0, self
.mtip
,
58 self
.ueip
, self
.seip
, 0, self
.meip
, )
61 if __name__
== "__main__":
63 print(verilog
.convert(example
,