cr_file.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity cr_file is
   9     generic (
  10         SIM : boolean := false
  11         );
  12     port(
  13         clk   : in std_logic;
  14
  15         d_in  : in Decode2ToCrFileType;
  16         d_out : out CrFileToDecode2Type;
  17
  18         w_in  : in WritebackToCrFileType;
  19
  20         -- debug
  21         sim_dump : in std_ulogic;
  22
  23         log_out : out std_ulogic_vector(12 downto 0)
  24         );
  25 end entity cr_file;
  26
  27 architecture behaviour of cr_file is
  28     signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
  29     signal crs_updated : std_ulogic_vector(31 downto 0);
  30     signal xerc : xer_common_t := xerc_init;
  31     signal xerc_updated : xer_common_t;
  32     signal log_data : std_ulogic_vector(12 downto 0);
  33 begin
  34     cr_create_0: process(all)
  35         variable hi, lo : integer := 0;
  36         variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
  37     begin
  38         cr_tmp := crs;
  39
  40         for i in 0 to 7 loop
  41             if w_in.write_cr_mask(i) = '1' then
  42                 lo := i*4;
  43                 hi := lo + 3;
  44                 cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
  45             end if;
  46         end loop;
  47
  48         crs_updated <= cr_tmp;
  49
  50         if w_in.write_xerc_enable = '1' then
  51             xerc_updated <= w_in.write_xerc_data;
  52         else
  53             xerc_updated <= xerc;
  54         end if;
  55
  56     end process;
  57
  58     -- synchronous writes
  59     cr_write_0: process(clk)
  60     begin
  61         if rising_edge(clk) then
  62             if w_in.write_cr_enable = '1' then
  63                 report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
  64                 crs <= crs_updated;
  65             end if;
  66             if w_in.write_xerc_enable = '1' then
  67                 report "Writing XERC";
  68                 xerc <= xerc_updated;
  69             end if;
  70         end if;
  71     end process;
  72
  73     -- asynchronous reads
  74     cr_read_0: process(all)
  75     begin
  76         -- just return the entire CR to make mfcrf easier for now
  77         if d_in.read = '1' then
  78             report "Reading CR " & to_hstring(crs_updated);
  79         end if;
  80         d_out.read_cr_data <= crs_updated;
  81         d_out.read_xerc_data <= xerc_updated;
  82     end process;
  83
  84     sim_dump_test: if SIM generate
  85         dump_cr: process(all)
  86         begin
  87             if sim_dump = '1' then
  88                 report "CR 00000000" & to_hstring(crs);
  89                 assert false report "end of test" severity failure;
  90             end if;
  91         end process;
  92     end generate;
  93
  94     cr_log: process(clk)
  95     begin
  96         if rising_edge(clk) then
  97             log_data <= w_in.write_cr_enable &
  98                         w_in.write_cr_data(31 downto 28) &
  99                         w_in.write_cr_mask;
 100         end if;
 101     end process;
 102     log_out <= log_data;
 103
 104 end architecture behaviour;