2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 PIPELINE_DEPTH : natural := 2
11 stall_in : in std_ulogic;
13 cr_read_in : in std_ulogic;
14 cr_write_in : in std_ulogic;
16 stall_out : out std_ulogic
19 architecture behaviour of cr_hazard is
20 type pipeline_entry_type is record
23 constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
25 type pipeline_t is array(0 to PIPELINE_DEPTH-1) of pipeline_entry_type;
26 constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
28 signal r, rin : pipeline_t := pipeline_t_init;
30 cr_hazard0: process(clk)
32 if rising_edge(clk) then
33 if stall_in = '0' then
39 cr_hazard1: process(all)
40 variable v : pipeline_t;
45 loop_0: for i in 0 to PIPELINE_DEPTH-1 loop
46 if (r(i).valid = cr_read_in) then
51 v(0).valid := cr_write_in;
52 loop_1: for i in 0 to PIPELINE_DEPTH-2 loop
53 -- propagate to next slot
57 -- asynchronous output
58 if cr_read_in = '0' then