crhelpers.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6
   7 package crhelpers is
   8     function fxm_to_num(fxm: std_ulogic_vector(7 downto 0)) return integer;
   9     function num_to_fxm(num: integer) return std_ulogic_vector;
  10 end package crhelpers;
  11
  12 package body crhelpers is
  13
  14     function fxm_to_num(fxm: std_ulogic_vector(7 downto 0)) return integer is
  15     begin
  16         -- If multiple fields are set (undefined), match existing
  17         -- hardware by returning the first one.
  18         for i in 0 to 7 loop
  19             -- Big endian bit numbering
  20             if fxm(7-i) = '1' then
  21                 return i;
  22             end if;
  23         end loop;
  24
  25         -- If no fields are set (undefined), also match existing
  26         -- hardware by returning cr7.
  27         return 7;
  28     end;
  29
  30     function num_to_fxm(num: integer) return std_ulogic_vector is
  31     begin
  32         case num is
  33             when 0 =>
  34                 return "10000000";
  35             when 1 =>
  36                 return "01000000";
  37             when 2 =>
  38                 return "00100000";
  39             when 3 =>
  40                 return "00010000";
  41             when 4 =>
  42                 return "00001000";
  43             when 5 =>
  44                 return "00000100";
  45             when 6 =>
  46                 return "00000010";
  47             when 7 =>
  48                 return "00000001";
  49             when others =>
  50                 return "00000000";
  51         end case;
  52     end;
  53
  54 end package body crhelpers;