3 <img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
4 <img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span> </span>
5 <img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
7 **This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
9 **This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
11 * NLnet page: [[nlnet_2021_crypto_router]]
12 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
13 * ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
17 All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
19 * 300 mhz single-core,
20 [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
22 [[openpower/sv/bitmanip]] extensions
24 * 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
25 [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
27 * 2x USB [[shakti/m_class/ULPI]] PHYs
28 * Direct DMA interface (independent bulk transfer)
29 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
30 GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
31 * On-board Dual-ported SRAM (for Packet Buffers)
32 * Opencores [[shakti/m_class/sdram]]
33 * Wishbone interfaces to all peripherals
34 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
39 # Example packet transfer
41 * Packet comes in on RGMII port 1. Each PHY has its own dual-ported SRAM
42 * Packet is **directly** stored in internal (dual-ported SRAM) by
44 * Interrupt notification is sent to the processor (XICS)
45 * Processor inspects packet over Wishbone interface directly
46 connected to 2nd SRAM port.
47 * Processor computes, based on decoding the ETH Frame, where the
48 packet must be sent to (which other RGM-II port: e.g. Port 2)
49 * Processor initiates Memory-to-Memory DMA transfer
50 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
51 from one on-board SRAM to the target on-board SRAM associated with Port 2.
52 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
53 * Processor notifies target RGM-II PHY to activate "send" of frame out
54 through target RGM-II port 2.
56 # Testing and Verification
58 We will need full HDL simulations as well as post P&R simulations.
59 These may be achieved as follows:
61 * ISA-level unit tests as well as Formal Correctness Proofs.
62 Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
63 and individual unit tests for the
64 [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
66 with some peripherals developed in c++ as verilator modules
67 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
69 [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
70 * [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
73 Actual instructions being developed (bitmanip) may therefore be
74 unit tested prior to deployment. Following that, rapid simulations
75 may be achieved by running Litex (the same HDL may also easily
76 be uploaded to an FPGA). When it comes to Place-and-Route of the
77 ASIC, the cocotb simulations may be used to verify that the GDS-II
78 layout has not been "damaged" by the PnR tools.
80 Peripherals functionality tests must also be part of the simulations,
81 particularly using cocotb, to ensure that they remain functional after PnR.
82 Supercomputer access for compilation of verilator and/or cxxrtl is available