crypto_router_asic.mdwn

   1 # Crypto-router ASIC
   2
   3 * NLnet page: [[nlnet_2021_crypto_router]]
   4 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
   5
   6 # Specifications:
   7
   8 All of these are entirely Libre-Licensed:
   9
  10 * 300 mhz single-core,
  11   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  12   OpenPOWER CPU with
  13   [[openpower/sv/bitmanip]] extensions
  14 * 180/130 nm (TBD)
  15 * 5x [[shakhti/m_class/RGMII]] Gigabit Ethernet PHYs
  16 * 2x USB [[shakhti/m_class/ULPI]] PHYs
  17 * Direct DMA interface (independent bulk transfer)
  18 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  19   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  20 * On-board Dual-ported SRAM (for Packet Buffers)
  21 * Opencores [[shakhti/m_class/sdram]]
  22 * Wishbone interfaces to all peripherals
  23 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  24   Interrupt Controller
  25
  26 # Example packet transfer:
  27
  28 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
  29 * Packet is **directly** stored in internal (dual-ported SRAM) by
  30   the RGMII PHY itself
  31 * Interrupt notification is sent to the processor (XICS)
  32 * Processor inspects packet over Wishbone interface directly
  33   connected to 2nd SRAM port.
  34 * Processor computes, based on decoding the ETH Frame, where the
  35   packet must be sent to (which other RGM-II port: e.g. Port 2)
  36 * Processor initiates Memory-to-Memory DMA transfer
  37 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  38   from one on-board SRAM to the target on-board SRAM associated with Port 2.
  39 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  40 * Processor notifies target RGM-II PHY to activate "send" of frame out
  41   through target RGM-II port 2.
  42