crypto_router_asic.mdwn

   1 # Crypto-router ASIC
   2
   3 * NLnet page: [[nlnet_2021_crypto_router]]
   4 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
   5
   6 # Specifications:
   7
   8 All of these are entirely Libre-Licensed:
   9
  10 * 300 mhz single-core,
  11   [Libre-SOC](https://git.libre-soc.org/?p=soc.git;a=blob;f=README.md;hb=HEAD)
  12   OpenPOWER CPU with
  13   [[openpower/sv/bitmanip]] extensions
  14 * 180/130 nm (TBD)
  15 * 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
  16 * 2x USB [[shakti/m_class/ULPI]] PHYs
  17 * Direct DMA interface (independent bulk transfer)
  18 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
  19   GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC
  20 * On-board Dual-ported SRAM (for Packet Buffers)
  21 * Opencores [[shakti/m_class/sdram]]
  22 * Wishbone interfaces to all peripherals
  23 * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD)
  24   Interrupt Controller
  25
  26 # Example packet transfer:
  27
  28 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
  29 * Packet is **directly** stored in internal (dual-ported SRAM) by
  30   the RGMII PHY itself
  31 * Interrupt notification is sent to the processor (XICS)
  32 * Processor inspects packet over Wishbone interface directly
  33   connected to 2nd SRAM port.
  34 * Processor computes, based on decoding the ETH Frame, where the
  35   packet must be sent to (which other RGM-II port: e.g. Port 2)
  36 * Processor initiates Memory-to-Memory DMA transfer
  37 * DMA Memory-to-Memory transfer, using Wishbone Bus, copies the ETH Frame
  38   from one on-board SRAM to the target on-board SRAM associated with Port 2.
  39 * DMA Engine generates interrupt (XICS) to the CPU to say it is completed
  40 * Processor notifies target RGM-II PHY to activate "send" of frame out
  41   through target RGM-II port 2.
  42
  43 # Testing and Verification
  44
  45 We will need full HDL simulations as well as post P&R simulations.
  46 These may be achieved as follows:
  47
  48 * ISA-level unit tests as well as Formal Correctness Proofs.
  49   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
  50   and individual unit tests for the
  51   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
  52 * [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
  53   with some peripherals developed in c++ as verilator modules
  54 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
  55   this unit test,
  56   [test_issuer.py](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD)
  57 * [cocotb pre/post PnR](https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD) including GHDL, Icarus and Verilator
  58   (where best suited)
  59
  60 Actual instructions being developed (bitmanip) may therefore be
  61 unit tested prior to deployment.  Following that, rapid simulations
  62 may be achieved by running Litex (the same HDL may also easily
  63 be uploaded to an FPGA).  When it comes to Place-and-Route of the
  64 ASIC, the cocotb simulations may be used to verify that the GDS-II
  65 layout has not been "damaged" by the PnR tools.