2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
19 use work.wishbone_types.all;
24 LINE_SIZE : positive := 64;
25 -- Number of lines in a set
26 NUM_LINES : positive := 32;
28 NUM_WAYS : positive := 4;
29 -- L1 DTLB entries per set
30 TLB_SET_SIZE : positive := 64;
31 -- L1 DTLB number of sets
32 TLB_NUM_WAYS : positive := 2;
33 -- L1 DTLB log_2(page_size)
34 TLB_LG_PGSZ : positive := 12
40 d_in : in Loadstore1ToDcacheType;
41 d_out : out DcacheToLoadstore1Type;
43 m_in : in MmuToDcacheType;
44 m_out : out DcacheToMmuType;
46 stall_out : out std_ulogic;
48 wishbone_out : out wishbone_master_out;
49 wishbone_in : in wishbone_slave_out;
51 log_out : out std_ulogic_vector(19 downto 0)
55 architecture rtl of dcache is
56 -- BRAM organisation: We never access more than wishbone_data_bits at
57 -- a time so to save resources we make the array only that wide, and
58 -- use consecutive indices for to make a cache "line"
60 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
61 constant ROW_SIZE : natural := wishbone_data_bits / 8;
62 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
63 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
64 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
66 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
68 -- Bit fields counts in the address
70 -- REAL_ADDR_BITS is the number of real address bits that we store
71 constant REAL_ADDR_BITS : positive := 56;
72 -- ROW_BITS is the number of bits to select a row
73 constant ROW_BITS : natural := log2(BRAM_ROWS);
74 -- ROW_LINEBITS is the number of bits to select a row within a line
75 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
76 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
77 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
78 -- ROW_OFF_BITS is the number of bits for the offset in a row
79 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
80 -- INDEX_BITS is the number if bits to select a cache line
81 constant INDEX_BITS : natural := log2(NUM_LINES);
82 -- SET_SIZE_BITS is the log base 2 of the set size
83 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
84 -- TAG_BITS is the number of bits of the tag part of the address
85 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
86 -- TAG_WIDTH is the width in bits of each way of the tag RAM
87 constant TAG_WIDTH : natural := TAG_BITS + 7 - ((TAG_BITS + 7) mod 8);
88 -- WAY_BITS is the number of bits to select a way
89 constant WAY_BITS : natural := log2(NUM_WAYS);
91 -- Example of layout for 32 lines of 64 bytes:
93 -- .. tag |index| line |
95 -- .. | |---| | ROW_LINEBITS (3)
96 -- .. | |--- - --| LINE_OFF_BITS (6)
97 -- .. | |- --| ROW_OFF_BITS (3)
98 -- .. |----- ---| | ROW_BITS (8)
99 -- .. |-----| | INDEX_BITS (5)
100 -- .. --------| | TAG_BITS (45)
102 subtype row_t is integer range 0 to BRAM_ROWS-1;
103 subtype index_t is integer range 0 to NUM_LINES-1;
104 subtype way_t is integer range 0 to NUM_WAYS-1;
105 subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
107 -- The cache data BRAM organized as described above for each way
108 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
110 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
111 -- not handle a clean (commented) definition of the cache tags as a 3d
112 -- memory. For now, work around it by putting all the tags
113 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
114 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
115 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
116 constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
117 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
118 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
120 -- The cache valid bits
121 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
122 type cache_valids_t is array(index_t) of cache_way_valids_t;
123 type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
125 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
126 signal cache_tags : cache_tags_array_t;
127 signal cache_tag_set : cache_tags_set_t;
128 signal cache_valids : cache_valids_t;
130 attribute ram_style : string;
131 attribute ram_style of cache_tags : signal is "distributed";
134 constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
135 constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
136 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
137 constant TLB_TAG_WAY_BITS : natural := TLB_NUM_WAYS * TLB_EA_TAG_BITS;
138 constant TLB_PTE_BITS : natural := 64;
139 constant TLB_PTE_WAY_BITS : natural := TLB_NUM_WAYS * TLB_PTE_BITS;
141 subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
142 subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
143 subtype tlb_way_valids_t is std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
144 type tlb_valids_t is array(tlb_index_t) of tlb_way_valids_t;
145 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
146 subtype tlb_way_tags_t is std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
147 type tlb_tags_t is array(tlb_index_t) of tlb_way_tags_t;
148 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
149 subtype tlb_way_ptes_t is std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
150 type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
151 type hit_way_set_t is array(tlb_way_t) of way_t;
153 signal dtlb_valids : tlb_valids_t;
154 signal dtlb_tags : tlb_tags_t;
155 signal dtlb_ptes : tlb_ptes_t;
156 attribute ram_style of dtlb_tags : signal is "distributed";
157 attribute ram_style of dtlb_ptes : signal is "distributed";
159 -- Record for storing permission, attribute, etc. bits from a PTE
160 type perm_attr_t is record
161 reference : std_ulogic;
162 changed : std_ulogic;
163 nocache : std_ulogic;
165 rd_perm : std_ulogic;
166 wr_perm : std_ulogic;
169 function extract_perm_attr(pte : std_ulogic_vector(TLB_PTE_BITS - 1 downto 0)) return perm_attr_t is
170 variable pa : perm_attr_t;
172 pa.reference := pte(8);
173 pa.changed := pte(7);
174 pa.nocache := pte(5);
176 pa.rd_perm := pte(2);
177 pa.wr_perm := pte(1);
181 constant real_mode_perm_attr : perm_attr_t := (nocache => '0', others => '1');
183 -- Type of operation on a "valid" input
184 type op_t is (OP_NONE,
185 OP_BAD, -- NC cache hit, TLB miss, prot/RC failure
186 OP_STCX_FAIL, -- conditional store w/o reservation
187 OP_LOAD_HIT, -- Cache hit on load
188 OP_LOAD_MISS, -- Load missing cache
189 OP_LOAD_NC, -- Non-cachable load
190 OP_STORE_HIT, -- Store hitting cache
191 OP_STORE_MISS); -- Store missing cache
193 -- Cache state machine
194 type state_t is (IDLE, -- Normal load hit processing
195 RELOAD_WAIT_ACK, -- Cache reload wait ack
196 STORE_WAIT_ACK, -- Store wait ack
197 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
201 -- Dcache operations:
203 -- In order to make timing, we use the BRAMs with an output buffer,
204 -- which means that the BRAM output is delayed by an extra cycle.
206 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
209 -- All other operations are handled via stalling in the first stage.
211 -- The second stage can thus complete a hit at the same time as the
212 -- first stage emits a stall for a complex op.
215 -- Stage 0 register, basically contains just the latched request
216 type reg_stage_0_t is record
217 req : Loadstore1ToDcacheType;
221 mmu_req : std_ulogic; -- indicates source of request
224 signal r0 : reg_stage_0_t;
225 signal r0_full : std_ulogic;
227 type mem_access_request_t is record
230 real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
231 data : std_ulogic_vector(63 downto 0);
232 byte_sel : std_ulogic_vector(7 downto 0);
234 same_tag : std_ulogic;
237 -- First stage register, contains state for stage 1 of load hits
238 -- and for the state machine used by all other operations
240 type reg_stage_1_t is record
241 -- Info about the request
242 full : std_ulogic; -- have uncompleted request
243 mmu_req : std_ulogic; -- request is from MMU
244 req : mem_access_request_t;
248 hit_load_valid : std_ulogic;
250 cache_hit : std_ulogic;
253 tlb_hit : std_ulogic;
254 tlb_hit_way : tlb_way_t;
255 tlb_hit_index : tlb_index_t;
257 -- 2-stage data buffer for data forwarded from writes to reads
258 forward_data1 : std_ulogic_vector(63 downto 0);
259 forward_data2 : std_ulogic_vector(63 downto 0);
260 forward_sel1 : std_ulogic_vector(7 downto 0);
261 forward_valid1 : std_ulogic;
262 forward_way1 : way_t;
263 forward_row1 : row_t;
264 use_forward1 : std_ulogic;
265 forward_sel : std_ulogic_vector(7 downto 0);
267 -- Cache miss state (reload state machine)
270 write_bram : std_ulogic;
271 write_tag : std_ulogic;
272 slow_valid : std_ulogic;
273 wb : wishbone_master_out;
274 reload_tag : cache_tag_t;
277 store_index : index_t;
278 end_row_ix : row_in_line_t;
279 rows_valid : row_per_line_valid_t;
280 acks_pending : unsigned(2 downto 0);
282 -- Signals to complete with error
283 error_done : std_ulogic;
284 cache_paradox : std_ulogic;
286 -- Signal to complete a failed stcx.
287 stcx_fail : std_ulogic;
289 -- completion signal for tlbie
290 tlbie_done : std_ulogic;
293 signal r1 : reg_stage_1_t;
295 -- Reservation information
297 type reservation_t is record
299 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
302 signal reservation : reservation_t;
304 -- Async signals on incoming request
305 signal req_index : index_t;
306 signal req_row : row_t;
307 signal req_hit_way : way_t;
308 signal req_tag : cache_tag_t;
309 signal req_op : op_t;
310 signal req_data : std_ulogic_vector(63 downto 0);
311 signal req_same_tag : std_ulogic;
313 signal early_req_row : row_t;
315 signal cancel_store : std_ulogic;
316 signal set_rsrv : std_ulogic;
317 signal clear_rsrv : std_ulogic;
319 signal r0_valid : std_ulogic;
320 signal r0_stall : std_ulogic;
322 signal use_forward1_next : std_ulogic;
323 signal use_forward2_next : std_ulogic;
325 -- Cache RAM interface
326 type cache_ram_out_t is array(way_t) of cache_row_t;
327 signal cache_out : cache_ram_out_t;
329 -- PLRU output interface
330 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
331 signal plru_victim : plru_out_t;
332 signal replace_way : way_t;
334 -- Wishbone read/write/cache write formatting signals
335 signal bus_sel : std_ulogic_vector(7 downto 0);
338 signal tlb_tag_way : tlb_way_tags_t;
339 signal tlb_pte_way : tlb_way_ptes_t;
340 signal tlb_valid_way : tlb_way_valids_t;
341 signal tlb_req_index : tlb_index_t;
342 signal tlb_hit : std_ulogic;
343 signal tlb_hit_way : tlb_way_t;
344 signal pte : tlb_pte_t;
345 signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
346 signal valid_ra : std_ulogic;
347 signal perm_attr : perm_attr_t;
348 signal rc_ok : std_ulogic;
349 signal perm_ok : std_ulogic;
350 signal access_ok : std_ulogic;
352 -- TLB PLRU output interface
353 type tlb_plru_out_t is array(tlb_index_t) of std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
354 signal tlb_plru_victim : tlb_plru_out_t;
357 -- Helper functions to decode incoming requests
360 -- Return the cache line index (tag index) for an address
361 function get_index(addr: std_ulogic_vector) return index_t is
363 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
366 -- Return the cache row index (data memory) for an address
367 function get_row(addr: std_ulogic_vector) return row_t is
369 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
372 -- Return the index of a row within a line
373 function get_row_of_line(row: row_t) return row_in_line_t is
374 variable row_v : unsigned(ROW_BITS-1 downto 0);
376 row_v := to_unsigned(row, ROW_BITS);
377 return row_v(ROW_LINEBITS-1 downto 0);
380 -- Returns whether this is the last row of a line
381 function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
383 return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
386 -- Returns whether this is the last row of a line
387 function is_last_row(row: row_t; last: row_in_line_t) return boolean is
389 return get_row_of_line(row) = last;
392 -- Return the address of the next row in the current cache line
393 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
394 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
395 variable result : wishbone_addr_type;
397 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
398 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
399 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
401 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
405 -- Return the next row in the current cache line. We use a dedicated
406 -- function in order to limit the size of the generated adder to be
407 -- only the bits within a cache line (3 bits with default settings)
409 function next_row(row: row_t) return row_t is
410 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
411 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
412 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
414 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
415 row_idx := row_v(ROW_LINEBITS-1 downto 0);
416 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
417 return to_integer(unsigned(row_v));
420 -- Get the tag value from the address
421 function get_tag(addr: std_ulogic_vector) return cache_tag_t is
423 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
426 -- Read a tag from a tag memory row
427 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
429 return tagset(way * TAG_WIDTH + TAG_BITS - 1 downto way * TAG_WIDTH);
432 -- Read a TLB tag from a TLB tag memory row
433 function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is
434 variable j : integer;
436 j := way * TLB_EA_TAG_BITS;
437 return tags(j + TLB_EA_TAG_BITS - 1 downto j);
440 -- Write a TLB tag to a TLB tag memory row
441 procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
443 variable j : integer;
445 j := way * TLB_EA_TAG_BITS;
446 tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
449 -- Read a PTE from a TLB PTE memory row
450 function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is
451 variable j : integer;
453 j := way * TLB_PTE_BITS;
454 return ptes(j + TLB_PTE_BITS - 1 downto j);
457 procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
458 variable j : integer;
460 j := way * TLB_PTE_BITS;
461 ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
464 signal log_data : std_ulogic_vector(19 downto 0);
468 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
469 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
470 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
471 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
472 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
473 report "geometry bits don't add up" severity FAILURE;
474 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
475 report "geometry bits don't add up" severity FAILURE;
476 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
477 report "geometry bits don't add up" severity FAILURE;
478 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
479 report "geometry bits don't add up" severity FAILURE;
480 assert (64 = wishbone_data_bits)
481 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
482 assert SET_SIZE_BITS <= TLB_LG_PGSZ report "Set indexed by virtual address" severity FAILURE;
484 -- Latch the request in r0.req as long as we're not stalling
485 stage_0 : process(clk)
486 variable r : reg_stage_0_t;
488 if rising_edge(clk) then
489 assert (d_in.valid and m_in.valid) = '0' report
490 "request collision loadstore vs MMU";
491 if m_in.valid = '1' then
493 r.req.load := not (m_in.tlbie or m_in.tlbld);
496 r.req.reserve := '0';
497 r.req.virt_mode := '0';
498 r.req.priv_mode := '1';
499 r.req.addr := m_in.addr;
500 r.req.data := m_in.pte;
501 r.req.byte_sel := (others => '1');
502 r.tlbie := m_in.tlbie;
503 r.doall := m_in.doall;
504 r.tlbld := m_in.tlbld;
515 elsif r1.full = '0' or r0_full = '0' then
517 r0_full <= r.req.valid;
522 -- we don't yet handle collisions between loadstore1 requests and MMU requests
525 -- Hold off the request in r0 when r1 has an uncompleted request
526 r0_stall <= r0_full and r1.full;
527 r0_valid <= r0_full and not r1.full;
528 stall_out <= r0_stall;
531 -- Operates in the second cycle on the request latched in r0.req.
532 -- TLB updates write the entry at the end of the second cycle.
533 tlb_read : process(clk)
534 variable index : tlb_index_t;
535 variable addrbits : std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
537 if rising_edge(clk) then
538 if m_in.valid = '1' then
539 addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
541 addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
543 index := to_integer(unsigned(addrbits));
544 -- If we have any op and the previous op isn't finished,
545 -- then keep the same output for next cycle.
546 if r0_stall = '0' then
547 tlb_valid_way <= dtlb_valids(index);
548 tlb_tag_way <= dtlb_tags(index);
549 tlb_pte_way <= dtlb_ptes(index);
554 -- Generate TLB PLRUs
555 maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
557 tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
558 -- TLB PLRU interface
559 signal tlb_plru_acc : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
560 signal tlb_plru_acc_en : std_ulogic;
561 signal tlb_plru_out : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
563 tlb_plru : entity work.plru
571 acc_en => tlb_plru_acc_en,
578 if r1.tlb_hit_index = i then
579 tlb_plru_acc_en <= r1.tlb_hit;
581 tlb_plru_acc_en <= '0';
583 tlb_plru_acc <= std_ulogic_vector(to_unsigned(r1.tlb_hit_way, TLB_WAY_BITS));
584 tlb_plru_victim(i) <= tlb_plru_out;
589 tlb_search : process(all)
590 variable hitway : tlb_way_t;
591 variable hit : std_ulogic;
592 variable eatag : tlb_tag_t;
594 tlb_req_index <= to_integer(unsigned(r0.req.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1
595 downto TLB_LG_PGSZ)));
598 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
599 for i in tlb_way_t loop
600 if tlb_valid_way(i) = '1' and
601 read_tlb_tag(i, tlb_tag_way) = eatag then
606 tlb_hit <= hit and r0_valid;
607 tlb_hit_way <= hitway;
608 if tlb_hit = '1' then
609 pte <= read_tlb_pte(hitway, tlb_pte_way);
611 pte <= (others => '0');
613 valid_ra <= tlb_hit or not r0.req.virt_mode;
614 if r0.req.virt_mode = '1' then
615 ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
616 r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
617 (ROW_OFF_BITS-1 downto 0 => '0');
618 perm_attr <= extract_perm_attr(pte);
620 ra <= r0.req.addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
621 (ROW_OFF_BITS-1 downto 0 => '0');
622 perm_attr <= real_mode_perm_attr;
626 tlb_update : process(clk)
627 variable tlbie : std_ulogic;
628 variable tlbwe : std_ulogic;
629 variable repl_way : tlb_way_t;
630 variable eatag : tlb_tag_t;
631 variable tagset : tlb_way_tags_t;
632 variable pteset : tlb_way_ptes_t;
634 if rising_edge(clk) then
635 tlbie := r0_valid and r0.tlbie;
636 tlbwe := r0_valid and r0.tlbld;
637 if rst = '1' or (tlbie = '1' and r0.doall = '1') then
638 -- clear all valid bits at once
639 for i in tlb_index_t loop
640 dtlb_valids(i) <= (others => '0');
642 elsif tlbie = '1' then
643 if tlb_hit = '1' then
644 dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
646 elsif tlbwe = '1' then
647 if tlb_hit = '1' then
648 repl_way := tlb_hit_way;
650 repl_way := to_integer(unsigned(tlb_plru_victim(tlb_req_index)));
652 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
653 tagset := tlb_tag_way;
654 write_tlb_tag(repl_way, tagset, eatag);
655 dtlb_tags(tlb_req_index) <= tagset;
656 pteset := tlb_pte_way;
657 write_tlb_pte(repl_way, pteset, r0.req.data);
658 dtlb_ptes(tlb_req_index) <= pteset;
659 dtlb_valids(tlb_req_index)(repl_way) <= '1';
665 maybe_plrus: if NUM_WAYS > 1 generate
667 plrus: for i in 0 to NUM_LINES-1 generate
669 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
670 signal plru_acc_en : std_ulogic;
671 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
674 plru : entity work.plru
682 acc_en => plru_acc_en,
689 if r1.hit_index = i then
690 plru_acc_en <= r1.cache_hit;
694 plru_acc <= std_ulogic_vector(to_unsigned(r1.hit_way, WAY_BITS));
695 plru_victim(i) <= plru_out;
700 -- Cache tag RAM read port
701 cache_tag_read : process(clk)
702 variable index : index_t;
704 if rising_edge(clk) then
705 if r0_stall = '1' then
707 elsif m_in.valid = '1' then
708 index := get_index(m_in.addr);
710 index := get_index(d_in.addr);
712 cache_tag_set <= cache_tags(index);
716 -- Cache request parsing and hit detection
717 dcache_request : process(all)
718 variable is_hit : std_ulogic;
719 variable hit_way : way_t;
721 variable opsel : std_ulogic_vector(2 downto 0);
722 variable go : std_ulogic;
723 variable nc : std_ulogic;
724 variable s_hit : std_ulogic;
725 variable s_tag : cache_tag_t;
726 variable s_pte : tlb_pte_t;
727 variable s_ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
728 variable hit_set : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
729 variable hit_way_set : hit_way_set_t;
730 variable rel_matches : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
731 variable rel_match : std_ulogic;
733 -- Extract line, row and tag from request
734 req_index <= get_index(r0.req.addr);
735 req_row <= get_row(r0.req.addr);
736 req_tag <= get_tag(ra);
738 go := r0_valid and not (r0.tlbie or r0.tlbld) and not r1.error_done;
740 -- Test if pending request is a hit on any way
741 -- In order to make timing in virtual mode, when we are using the TLB,
742 -- we compare each way with each of the real addresses from each way of
743 -- the TLB, and then decide later which match to use.
747 if r0.req.virt_mode = '1' then
748 rel_matches := (others => '0');
749 for j in tlb_way_t loop
752 s_pte := read_tlb_pte(j, tlb_pte_way);
753 s_ra := s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
754 r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
755 s_tag := get_tag(s_ra);
757 if go = '1' and cache_valids(req_index)(i) = '1' and
758 read_tag(i, cache_tag_set) = s_tag and
759 tlb_valid_way(j) = '1' then
765 if s_tag = r1.reload_tag then
766 rel_matches(j) := '1';
769 if tlb_hit = '1' then
770 is_hit := hit_set(tlb_hit_way);
771 hit_way := hit_way_set(tlb_hit_way);
772 rel_match := rel_matches(tlb_hit_way);
775 s_tag := get_tag(r0.req.addr);
777 if go = '1' and cache_valids(req_index)(i) = '1' and
778 read_tag(i, cache_tag_set) = s_tag then
783 if s_tag = r1.reload_tag then
787 req_same_tag <= rel_match;
789 -- See if the request matches the line currently being reloaded
790 if r1.state = RELOAD_WAIT_ACK and req_index = r1.store_index and
792 -- For a store, consider this a hit even if the row isn't valid
793 -- since it will be by the time we perform the store.
794 -- For a load, check the appropriate row valid bit.
795 is_hit := not r0.req.load or r1.rows_valid(req_row mod ROW_PER_LINE);
796 hit_way := replace_way;
799 -- Whether to use forwarded data for a load or not
800 use_forward1_next <= '0';
801 if get_row(r1.req.real_addr) = req_row and r1.req.hit_way = hit_way then
802 -- Only need to consider r1.write_bram here, since if we are
803 -- writing refill data here, then we don't have a cache hit this
804 -- cycle on the line being refilled. (There is the possibility
805 -- that the load following the load miss that started the refill
806 -- could be to the old contents of the victim line, since it is a
807 -- couple of cycles after the refill starts before we see the
808 -- updated cache tag. In that case we don't use the bypass.)
809 use_forward1_next <= r1.write_bram;
811 use_forward2_next <= '0';
812 if r1.forward_row1 = req_row and r1.forward_way1 = hit_way then
813 use_forward2_next <= r1.forward_valid1;
816 -- The way that matched on a hit
817 req_hit_way <= hit_way;
819 -- The way to replace on a miss
820 if r1.write_tag = '1' then
821 replace_way <= to_integer(unsigned(plru_victim(r1.store_index)));
823 replace_way <= r1.store_way;
826 -- work out whether we have permission for this access
827 -- NB we don't yet implement AMR, thus no KUAP
828 rc_ok <= perm_attr.reference and (r0.req.load or perm_attr.changed);
829 perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
830 (perm_attr.wr_perm or (r0.req.load and perm_attr.rd_perm));
831 access_ok <= valid_ra and perm_ok and rc_ok;
833 -- Combine the request and cache hit status to decide what
834 -- operation needs to be done
836 nc := r0.req.nc or perm_attr.nocache;
839 if access_ok = '0' then
841 elsif cancel_store = '1' then
844 opsel := r0.req.load & nc & is_hit;
846 when "101" => op := OP_LOAD_HIT;
847 when "100" => op := OP_LOAD_MISS;
848 when "110" => op := OP_LOAD_NC;
849 when "001" => op := OP_STORE_HIT;
850 when "000" => op := OP_STORE_MISS;
851 when "010" => op := OP_STORE_MISS;
852 when "011" => op := OP_BAD;
853 when "111" => op := OP_BAD;
854 when others => op := OP_NONE;
860 -- Version of the row number that is valid one cycle earlier
861 -- in the cases where we need to read the cache data BRAM.
862 -- If we're stalling then we need to keep reading the last
864 if r0_stall = '0' then
865 if m_in.valid = '1' then
866 early_req_row <= get_row(m_in.addr);
868 early_req_row <= get_row(d_in.addr);
871 early_req_row <= req_row;
875 -- Wire up wishbone request latch out of stage 1
876 wishbone_out <= r1.wb;
878 -- Handle load-with-reservation and store-conditional instructions
879 reservation_comb: process(all)
884 if r0_valid = '1' and r0.req.reserve = '1' then
885 -- XXX generate alignment interrupt if address is not aligned
886 -- XXX or if r0.req.nc = '1'
887 if r0.req.load = '1' then
888 -- load with reservation
893 if reservation.valid = '0' or
894 r0.req.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
901 reservation_reg: process(clk)
903 if rising_edge(clk) then
905 reservation.valid <= '0';
906 elsif r0_valid = '1' and access_ok = '1' then
907 if clear_rsrv = '1' then
908 reservation.valid <= '0';
909 elsif set_rsrv = '1' then
910 reservation.valid <= '1';
911 reservation.addr <= r0.req.addr(63 downto LINE_OFF_BITS);
917 -- Return data for loads & completion control logic
919 writeback_control: process(all)
920 variable data_out : std_ulogic_vector(63 downto 0);
921 variable data_fwd : std_ulogic_vector(63 downto 0);
922 variable j : integer;
924 -- Use the bypass if are reading the row that was written 1 or 2 cycles
925 -- ago, including for the slow_valid = 1 case (i.e. completing a load
926 -- miss or a non-cacheable load).
927 if r1.use_forward1 = '1' then
928 data_fwd := r1.forward_data1;
930 data_fwd := r1.forward_data2;
932 data_out := cache_out(r1.hit_way);
935 if r1.forward_sel(i) = '1' then
936 data_out(j + 7 downto j) := data_fwd(j + 7 downto j);
941 d_out.data <= data_out;
942 d_out.store_done <= '0';
944 d_out.cache_paradox <= '0';
947 m_out.done <= r1.tlbie_done;
949 m_out.data <= data_out;
951 -- We have a valid load or store hit or we just completed a slow
952 -- op such as a load miss, a NC load or a store
954 -- Note: the load hit is delayed by one cycle. However it can still
955 -- not collide with r.slow_valid (well unless I miscalculated) because
956 -- slow_valid can only be set on a subsequent request and not on its
957 -- first cycle (the state machine must have advanced), which makes
958 -- slow_valid at least 2 cycles from the previous hit_load_valid.
961 -- Sanity: Only one of these must be set in any given cycle
962 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
963 "unexpected slow_valid collision with stcx_fail"
965 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
966 "unexpected hit_load_delayed collision with slow_valid"
969 if r1.mmu_req = '0' then
970 -- Request came from loadstore1...
971 -- Load hit case is the standard path
972 if r1.hit_load_valid = '1' then
973 report "completing load hit data=" & to_hstring(data_out);
977 -- error cases complete without stalling
978 if r1.error_done = '1' then
979 report "completing ld/st with error";
981 d_out.cache_paradox <= r1.cache_paradox;
985 -- Slow ops (load miss, NC, stores)
986 if r1.slow_valid = '1' then
987 d_out.store_done <= '1';
988 report "completing store or load miss data=" & to_hstring(data_out);
992 if r1.stcx_fail = '1' then
993 d_out.store_done <= '0';
998 -- Request came from MMU
999 if r1.hit_load_valid = '1' then
1000 report "completing load hit to MMU, data=" & to_hstring(m_out.data);
1004 -- error cases complete without stalling
1005 if r1.error_done = '1' then
1006 report "completing MMU ld with error";
1011 -- Slow ops (i.e. load miss)
1012 if r1.slow_valid = '1' then
1013 report "completing MMU load miss, data=" & to_hstring(m_out.data);
1021 -- Generate a cache RAM for each way. This handles the normal
1022 -- reads, writes from reloads and the special store-hit update
1025 -- Note: the BRAMs have an extra read buffer, meaning the output
1026 -- is pipelined an extra cycle. This differs from the
1027 -- icache. The writeback logic needs to take that into
1028 -- account by using 1-cycle delayed signals for load hits.
1030 rams: for i in 0 to NUM_WAYS-1 generate
1031 signal do_read : std_ulogic;
1032 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1033 signal do_write : std_ulogic;
1034 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1035 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
1036 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
1037 signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
1038 signal dout : cache_row_t;
1040 way: entity work.cache_ram
1042 ROW_BITS => ROW_BITS,
1043 WIDTH => wishbone_data_bits,
1059 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
1060 cache_out(i) <= dout;
1064 -- Defaults to wishbone read responses (cache refill),
1066 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
1067 -- other than the current state.
1069 wr_sel_m <= (others => '0');
1072 if r1.write_bram = '1' then
1073 -- Write store data to BRAM. This happens one cycle after the
1075 wr_data <= r1.req.data;
1076 wr_sel <= r1.req.byte_sel;
1077 wr_addr <= std_ulogic_vector(to_unsigned(get_row(r1.req.real_addr), ROW_BITS));
1078 if i = r1.req.hit_way then
1082 -- Otherwise, we might be doing a reload or a DCBZ
1083 if r1.dcbz = '1' then
1084 wr_data <= (others => '0');
1086 wr_data <= wishbone_in.dat;
1088 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
1089 wr_sel <= (others => '1');
1091 if r1.state = RELOAD_WAIT_ACK and wishbone_in.ack = '1' and replace_way = i then
1096 -- Mask write selects with do_write since BRAM doesn't
1097 -- have a global write-enable
1098 if do_write = '1' then
1106 -- Cache hit synchronous machine for the easy case. This handles load hits.
1107 -- It also handles error cases (TLB miss, cache paradox)
1109 dcache_fast_hit : process(clk)
1111 if rising_edge(clk) then
1112 if req_op /= OP_NONE then
1113 report "op:" & op_t'image(req_op) &
1114 " addr:" & to_hstring(r0.req.addr) &
1115 " nc:" & std_ulogic'image(r0.req.nc) &
1116 " idx:" & integer'image(req_index) &
1117 " tag:" & to_hstring(req_tag) &
1118 " way: " & integer'image(req_hit_way);
1120 if r0_valid = '1' then
1121 r1.mmu_req <= r0.mmu_req;
1124 -- Fast path for load/store hits. Set signals for the writeback controls.
1125 r1.hit_way <= req_hit_way;
1126 r1.hit_index <= req_index;
1127 if req_op = OP_LOAD_HIT then
1128 r1.hit_load_valid <= '1';
1130 r1.hit_load_valid <= '0';
1132 if req_op = OP_LOAD_HIT or req_op = OP_STORE_HIT then
1133 r1.cache_hit <= '1';
1135 r1.cache_hit <= '0';
1138 if req_op = OP_BAD then
1139 report "Signalling ld/st error valid_ra=" & std_ulogic'image(valid_ra) &
1140 " rc_ok=" & std_ulogic'image(rc_ok) & " perm_ok=" & std_ulogic'image(perm_ok);
1141 r1.error_done <= '1';
1142 r1.cache_paradox <= access_ok;
1144 r1.error_done <= '0';
1145 r1.cache_paradox <= '0';
1148 if req_op = OP_STCX_FAIL then
1149 r1.stcx_fail <= '1';
1151 r1.stcx_fail <= '0';
1154 -- Record TLB hit information for updating TLB PLRU
1155 r1.tlb_hit <= tlb_hit;
1156 r1.tlb_hit_way <= tlb_hit_way;
1157 r1.tlb_hit_index <= tlb_req_index;
1159 -- complete tlbies and TLB loads in the third cycle
1160 r1.tlbie_done <= r0_valid and (r0.tlbie or r0.tlbld);
1165 -- Memory accesses are handled by this state machine:
1167 -- * Cache load miss/reload (in conjunction with "rams")
1168 -- * Load hits for non-cachable forms
1169 -- * Stores (the collision case is handled in "rams")
1171 -- All wishbone requests generation is done here. This machine
1172 -- operates at stage 1.
1174 dcache_slow : process(clk)
1175 variable stbs_done : boolean;
1176 variable req : mem_access_request_t;
1177 variable acks : unsigned(2 downto 0);
1179 if rising_edge(clk) then
1180 r1.use_forward1 <= use_forward1_next;
1181 r1.forward_sel <= (others => '0');
1182 if use_forward1_next = '1' then
1183 r1.forward_sel <= r1.req.byte_sel;
1184 elsif use_forward2_next = '1' then
1185 r1.forward_sel <= r1.forward_sel1;
1188 r1.forward_data2 <= r1.forward_data1;
1189 if r1.write_bram = '1' then
1190 r1.forward_data1 <= r1.req.data;
1191 r1.forward_sel1 <= r1.req.byte_sel;
1192 r1.forward_way1 <= r1.req.hit_way;
1193 r1.forward_row1 <= get_row(r1.req.real_addr);
1194 r1.forward_valid1 <= '1';
1196 if r1.dcbz = '1' then
1197 r1.forward_data1 <= (others => '0');
1199 r1.forward_data1 <= wishbone_in.dat;
1201 r1.forward_sel1 <= (others => '1');
1202 r1.forward_way1 <= replace_way;
1203 r1.forward_row1 <= r1.store_row;
1204 r1.forward_valid1 <= '0';
1207 -- On reset, clear all valid bits to force misses
1209 for i in index_t loop
1210 cache_valids(i) <= (others => '0');
1214 r1.slow_valid <= '0';
1218 -- Not useful normally but helps avoiding tons of sim warnings
1219 r1.wb.adr <= (others => '0');
1221 -- One cycle pulses reset
1222 r1.slow_valid <= '0';
1223 r1.write_bram <= '0';
1225 if r1.write_tag = '1' then
1226 -- Store new tag in selected way
1227 for i in 0 to NUM_WAYS-1 loop
1228 if i = replace_way then
1229 cache_tags(r1.store_index)((i + 1) * TAG_WIDTH - 1 downto i * TAG_WIDTH) <=
1230 (TAG_WIDTH - 1 downto TAG_BITS => '0') & r1.reload_tag;
1233 r1.store_way <= replace_way;
1234 r1.write_tag <= '0';
1237 -- Take request from r1.req if there is one there,
1238 -- else from req_op, ra, etc.
1239 if r1.full = '1' then
1243 req.dcbz := r0.req.dcbz;
1244 req.real_addr := ra;
1245 req.data := r0.req.data;
1246 req.byte_sel := r0.req.byte_sel;
1247 req.hit_way := req_hit_way;
1248 req.same_tag := req_same_tag;
1250 -- Store the incoming request from r0, if it is a slow request
1251 -- Note that r1.full = 1 implies req_op = OP_NONE
1252 if req_op = OP_LOAD_MISS or req_op = OP_LOAD_NC or
1253 req_op = OP_STORE_MISS or req_op = OP_STORE_HIT then
1259 -- Main state machine
1262 r1.wb.adr <= req.real_addr(r1.wb.adr'left downto 0);
1265 -- Keep track of our index and way for subsequent stores.
1266 r1.store_index <= get_index(req.real_addr);
1267 r1.store_row <= get_row(req.real_addr);
1268 r1.end_row_ix <= get_row_of_line(get_row(req.real_addr)) - 1;
1269 r1.reload_tag <= get_tag(req.real_addr);
1270 r1.req.same_tag <= '1';
1272 if req.op = OP_STORE_HIT then
1273 r1.store_way <= req.hit_way;
1276 -- Reset per-row valid bits, ready for handling OP_LOAD_MISS
1277 for i in 0 to ROW_PER_LINE - 1 loop
1278 r1.rows_valid(i) <= '0';
1283 -- stay in IDLE state
1285 when OP_LOAD_MISS =>
1286 -- Normal load cache miss, start the reload machine
1288 report "cache miss real addr:" & to_hstring(req.real_addr) &
1289 " idx:" & integer'image(get_index(req.real_addr)) &
1290 " tag:" & to_hstring(get_tag(req.real_addr));
1292 -- Start the wishbone cycle
1293 r1.wb.sel <= (others => '1');
1298 -- Track that we had one request sent
1299 r1.state <= RELOAD_WAIT_ACK;
1300 r1.write_tag <= '1';
1303 r1.wb.sel <= req.byte_sel;
1307 r1.state <= NC_LOAD_WAIT_ACK;
1309 when OP_STORE_HIT | OP_STORE_MISS =>
1310 if req.dcbz = '0' then
1311 r1.wb.sel <= req.byte_sel;
1312 r1.wb.dat <= req.data;
1313 r1.state <= STORE_WAIT_ACK;
1314 r1.acks_pending <= to_unsigned(1, 3);
1316 r1.slow_valid <= '1';
1317 if req.op = OP_STORE_HIT then
1318 r1.write_bram <= '1';
1321 -- dcbz is handled much like a load miss except
1322 -- that we are writing to memory instead of reading
1324 -- Start the wishbone writes
1325 r1.wb.sel <= (others => '1');
1326 r1.wb.dat <= (others => '0');
1328 -- Handle the rest like a load miss
1329 r1.state <= RELOAD_WAIT_ACK;
1330 if req.op = OP_STORE_MISS then
1331 r1.write_tag <= '1';
1339 -- OP_NONE and OP_BAD do nothing
1340 -- OP_BAD & OP_STCX_FAIL were handled above already
1343 when OP_STCX_FAIL =>
1346 when RELOAD_WAIT_ACK =>
1347 -- Requests are all sent if stb is 0
1348 stbs_done := r1.wb.stb = '0';
1350 -- If we are still sending requests, was one accepted ?
1351 if wishbone_in.stall = '0' and not stbs_done then
1352 -- That was the last word ? We are done sending. Clear
1353 -- stb and set stbs_done so we can handle an eventual last
1354 -- ack on the same cycle.
1356 if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then
1361 -- Calculate the next row address
1362 r1.wb.adr <= next_row_addr(r1.wb.adr);
1365 -- Incoming acks processing
1366 r1.forward_valid1 <= wishbone_in.ack;
1367 if wishbone_in.ack = '1' then
1368 r1.rows_valid(r1.store_row mod ROW_PER_LINE) <= '1';
1369 -- If this is the data we were looking for, we can
1370 -- complete the request next cycle.
1371 -- Compare the whole address in case the request in
1372 -- r1.req is not the one that started this refill.
1373 if r1.full = '1' and r1.req.same_tag = '1' and
1374 ((r1.dcbz = '1' and r1.req.dcbz = '1') or
1375 (r1.dcbz = '0' and r1.req.op = OP_LOAD_MISS)) and
1376 r1.store_row = get_row(r1.req.real_addr) then
1378 r1.slow_valid <= '1';
1379 r1.forward_sel <= (others => '1');
1380 r1.use_forward1 <= '1';
1383 -- Check for completion
1384 if stbs_done and is_last_row(r1.store_row, r1.end_row_ix) then
1385 -- Complete wishbone cycle
1388 -- Cache line is now valid
1389 cache_valids(r1.store_index)(r1.store_way) <= '1';
1394 -- Increment store row counter
1395 r1.store_row <= next_row(r1.store_row);
1398 when STORE_WAIT_ACK =>
1399 stbs_done := r1.wb.stb = '0';
1400 acks := r1.acks_pending;
1401 -- Clear stb when slave accepted request
1402 if wishbone_in.stall = '0' then
1403 -- See if there is another store waiting to be done
1404 -- which is in the same real page.
1405 if acks < 7 and req.same_tag = '1' and
1406 (req.op = OP_STORE_MISS or req.op = OP_STORE_HIT) then
1407 r1.wb.adr <= req.real_addr(r1.wb.adr'left downto 0);
1408 r1.wb.dat <= req.data;
1409 r1.wb.sel <= req.byte_sel;
1412 if req.op = OP_STORE_HIT then
1413 r1.write_bram <= '1';
1416 r1.slow_valid <= '1';
1424 -- Got ack ? See if complete.
1425 if wishbone_in.ack = '1' then
1426 if stbs_done and acks = 1 then
1433 r1.acks_pending <= acks;
1435 when NC_LOAD_WAIT_ACK =>
1436 -- Clear stb when slave accepted request
1437 if wishbone_in.stall = '0' then
1441 -- Got ack ? complete.
1442 if wishbone_in.ack = '1' then
1445 r1.slow_valid <= '1';
1446 r1.forward_sel <= (others => '1');
1447 r1.use_forward1 <= '1';
1456 dcache_log: process(clk)
1458 if rising_edge(clk) then
1459 log_data <= r1.wb.adr(5 downto 3) &
1462 r1.wb.stb & r1.wb.cyc &
1465 std_ulogic_vector(to_unsigned(op_t'pos(req_op), 3)) &
1467 std_ulogic_vector(to_unsigned(tlb_hit_way, 3)) &
1469 std_ulogic_vector(to_unsigned(state_t'pos(r1.state), 3));
1472 log_out <= log_data;