2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
19 use work.wishbone_types.all;
24 LINE_SIZE : positive := 64;
25 -- Number of lines in a set
26 NUM_LINES : positive := 32;
28 NUM_WAYS : positive := 4;
29 -- L1 DTLB entries per set
30 TLB_SET_SIZE : positive := 64;
31 -- L1 DTLB number of sets
32 TLB_NUM_WAYS : positive := 2;
33 -- L1 DTLB log_2(page_size)
34 TLB_LG_PGSZ : positive := 12
40 d_in : in Loadstore1ToDcacheType;
41 d_out : out DcacheToLoadstore1Type;
43 stall_out : out std_ulogic;
45 wishbone_out : out wishbone_master_out;
46 wishbone_in : in wishbone_slave_out
50 architecture rtl of dcache is
51 -- BRAM organisation: We never access more than wishbone_data_bits at
52 -- a time so to save resources we make the array only that wide, and
53 -- use consecutive indices for to make a cache "line"
55 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
56 constant ROW_SIZE : natural := wishbone_data_bits / 8;
57 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
58 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
59 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
61 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
63 -- Bit fields counts in the address
65 -- REAL_ADDR_BITS is the number of real address bits that we store
66 constant REAL_ADDR_BITS : positive := 56;
67 -- ROW_BITS is the number of bits to select a row
68 constant ROW_BITS : natural := log2(BRAM_ROWS);
69 -- ROW_LINEBITS is the number of bits to select a row within a line
70 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
71 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
72 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
73 -- ROW_OFF_BITS is the number of bits for the offset in a row
74 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
75 -- INDEX_BITS is the number if bits to select a cache line
76 constant INDEX_BITS : natural := log2(NUM_LINES);
77 -- SET_SIZE_BITS is the log base 2 of the set size
78 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
79 -- TAG_BITS is the number of bits of the tag part of the address
80 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
81 -- WAY_BITS is the number of bits to select a way
82 constant WAY_BITS : natural := log2(NUM_WAYS);
84 -- Example of layout for 32 lines of 64 bytes:
86 -- .. tag |index| line |
88 -- .. | |---| | ROW_LINEBITS (3)
89 -- .. | |--- - --| LINE_OFF_BITS (6)
90 -- .. | |- --| ROW_OFF_BITS (3)
91 -- .. |----- ---| | ROW_BITS (8)
92 -- .. |-----| | INDEX_BITS (5)
93 -- .. --------| | TAG_BITS (45)
95 subtype row_t is integer range 0 to BRAM_ROWS-1;
96 subtype index_t is integer range 0 to NUM_LINES-1;
97 subtype way_t is integer range 0 to NUM_WAYS-1;
99 -- The cache data BRAM organized as described above for each way
100 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
102 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
103 -- not handle a clean (commented) definition of the cache tags as a 3d
104 -- memory. For now, work around it by putting all the tags
105 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
106 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
107 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
108 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
109 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
110 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
112 -- The cache valid bits
113 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
114 type cache_valids_t is array(index_t) of cache_way_valids_t;
116 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
117 signal cache_tags : cache_tags_array_t;
118 signal cache_valids : cache_valids_t;
120 attribute ram_style : string;
121 attribute ram_style of cache_tags : signal is "distributed";
124 constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
125 constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
126 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
127 constant TLB_TAG_WAY_BITS : natural := TLB_NUM_WAYS * TLB_EA_TAG_BITS;
128 constant TLB_PTE_BITS : natural := 64;
129 constant TLB_PTE_WAY_BITS : natural := TLB_NUM_WAYS * TLB_PTE_BITS;
131 subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
132 subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
133 subtype tlb_way_valids_t is std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
134 type tlb_valids_t is array(tlb_index_t) of tlb_way_valids_t;
135 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
136 subtype tlb_way_tags_t is std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
137 type tlb_tags_t is array(tlb_index_t) of tlb_way_tags_t;
138 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
139 subtype tlb_way_ptes_t is std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
140 type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
141 type hit_way_set_t is array(tlb_way_t) of way_t;
143 signal dtlb_valids : tlb_valids_t;
144 signal dtlb_tags : tlb_tags_t;
145 signal dtlb_ptes : tlb_ptes_t;
146 attribute ram_style of dtlb_tags : signal is "distributed";
147 attribute ram_style of dtlb_ptes : signal is "distributed";
149 signal r0 : Loadstore1ToDcacheType;
150 signal r0_valid : std_ulogic;
152 -- Type of operation on a "valid" input
153 type op_t is (OP_NONE,
154 OP_LOAD_HIT, -- Cache hit on load
155 OP_LOAD_MISS, -- Load missing cache
156 OP_LOAD_NC, -- Non-cachable load
157 OP_BAD, -- BAD: Cache hit on NC load/store
158 OP_STORE_HIT, -- Store hitting cache
159 OP_STORE_MISS); -- Store missing cache
161 -- Cache state machine
162 type state_t is (IDLE, -- Normal load hit processing
163 RELOAD_WAIT_ACK, -- Cache reload wait ack
164 FINISH_LD_MISS, -- Extra cycle after load miss
165 STORE_WAIT_ACK, -- Store wait ack
166 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
170 -- Dcache operations:
172 -- In order to make timing, we use the BRAMs with an output buffer,
173 -- which means that the BRAM output is delayed by an extra cycle.
175 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
178 -- All other operations are handled via stalling in the first stage.
180 -- The second stage can thus complete a hit at the same time as the
181 -- first stage emits a stall for a complex op.
184 -- First stage register, contains state for stage 1 of load hits
185 -- and for the state machine used by all other operations
187 type reg_stage_1_t is record
188 -- Latch the complete request from ls1
189 req : Loadstore1ToDcacheType;
193 hit_load_valid : std_ulogic;
195 -- Data buffer for "slow" read ops (load miss and NC loads).
196 slow_data : std_ulogic_vector(63 downto 0);
197 slow_valid : std_ulogic;
199 -- Signal to complete a failed stcx.
200 stcx_fail : std_ulogic;
202 -- Cache miss state (reload state machine)
204 wb : wishbone_master_out;
207 store_index : index_t;
209 -- Signals to complete with error
210 error_done : std_ulogic;
211 tlb_miss : std_ulogic;
213 -- completion signal for tlbie
214 tlbie_done : std_ulogic;
217 signal r1 : reg_stage_1_t;
219 -- Reservation information
221 type reservation_t is record
223 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
226 signal reservation : reservation_t;
228 -- Async signals on incoming request
229 signal req_index : index_t;
230 signal req_row : row_t;
231 signal req_hit_way : way_t;
232 signal req_tag : cache_tag_t;
233 signal req_op : op_t;
234 signal req_data : std_ulogic_vector(63 downto 0);
235 signal req_laddr : std_ulogic_vector(63 downto 0);
237 signal early_req_row : row_t;
239 signal cancel_store : std_ulogic;
240 signal set_rsrv : std_ulogic;
241 signal clear_rsrv : std_ulogic;
243 -- Cache RAM interface
244 type cache_ram_out_t is array(way_t) of cache_row_t;
245 signal cache_out : cache_ram_out_t;
247 -- PLRU output interface
248 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
249 signal plru_victim : plru_out_t;
250 signal replace_way : way_t;
252 -- Wishbone read/write/cache write formatting signals
253 signal bus_sel : std_ulogic_vector(7 downto 0);
256 signal tlb_tag_way : tlb_way_tags_t;
257 signal tlb_pte_way : tlb_way_ptes_t;
258 signal tlb_valid_way : tlb_way_valids_t;
259 signal tlb_req_index : tlb_index_t;
260 signal tlb_hit : std_ulogic;
261 signal tlb_hit_way : tlb_way_t;
262 signal pte : tlb_pte_t;
263 signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
264 signal valid_ra : std_ulogic;
266 -- TLB PLRU output interface
267 type tlb_plru_out_t is array(tlb_index_t) of std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
268 signal tlb_plru_victim : tlb_plru_out_t;
271 -- Helper functions to decode incoming requests
274 -- Return the cache line index (tag index) for an address
275 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
277 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
280 -- Return the cache row index (data memory) for an address
281 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
283 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
286 -- Returns whether this is the last row of a line
287 function is_last_row_addr(addr: wishbone_addr_type) return boolean is
288 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
290 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
293 -- Returns whether this is the last row of a line
294 function is_last_row(row: row_t) return boolean is
295 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
296 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
298 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
299 return row_v(ROW_LINEBITS-1 downto 0) = ones;
302 -- Return the address of the next row in the current cache line
303 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
304 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
305 variable result : wishbone_addr_type;
307 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
308 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
309 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
311 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
315 -- Return the next row in the current cache line. We use a dedicated
316 -- function in order to limit the size of the generated adder to be
317 -- only the bits within a cache line (3 bits with default settings)
319 function next_row(row: row_t) return row_t is
320 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
321 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
322 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
324 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
325 row_idx := row_v(ROW_LINEBITS-1 downto 0);
326 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
327 return to_integer(unsigned(row_v));
330 -- Get the tag value from the address
331 function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)) return cache_tag_t is
333 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
336 -- Read a tag from a tag memory row
337 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
339 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
342 -- Write a tag to tag memory row
343 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
346 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
349 -- Read a TLB tag from a TLB tag memory row
350 function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is
351 variable j : integer;
353 j := way * TLB_EA_TAG_BITS;
354 return tags(j + TLB_EA_TAG_BITS - 1 downto j);
357 -- Write a TLB tag to a TLB tag memory row
358 procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
360 variable j : integer;
362 j := way * TLB_EA_TAG_BITS;
363 tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
366 -- Read a PTE from a TLB PTE memory row
367 function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is
368 variable j : integer;
370 j := way * TLB_PTE_BITS;
371 return ptes(j + TLB_PTE_BITS - 1 downto j);
374 procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
375 variable j : integer;
377 j := way * TLB_PTE_BITS;
378 ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
383 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
384 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
385 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
386 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
387 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
388 report "geometry bits don't add up" severity FAILURE;
389 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
390 report "geometry bits don't add up" severity FAILURE;
391 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
392 report "geometry bits don't add up" severity FAILURE;
393 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
394 report "geometry bits don't add up" severity FAILURE;
395 assert (64 = wishbone_data_bits)
396 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
398 -- Latch the request in r0 as long as we're not stalling
399 stage_0 : process(clk)
401 if rising_edge(clk) then
404 elsif stall_out = '0' then
410 -- Hold off the request in r0 when stalling,
411 -- and cancel it if we get an error in a previous request.
412 r0_valid <= r0.valid and not stall_out and not r1.error_done;
415 -- Operates in the second cycle on the request latched in r0.
416 -- TLB updates write the entry at the end of the second cycle.
417 tlb_read : process(clk)
418 variable index : tlb_index_t;
420 if rising_edge(clk) then
421 if stall_out = '1' then
422 -- keep reading the same thing while stalled
423 index := tlb_req_index;
425 index := to_integer(unsigned(d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1
426 downto TLB_LG_PGSZ)));
428 tlb_valid_way <= dtlb_valids(index);
429 tlb_tag_way <= dtlb_tags(index);
430 tlb_pte_way <= dtlb_ptes(index);
434 -- Generate TLB PLRUs
435 maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
437 tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
438 -- TLB PLRU interface
439 signal tlb_plru_acc : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
440 signal tlb_plru_acc_en : std_ulogic;
441 signal tlb_plru_out : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
443 tlb_plru : entity work.plru
451 acc_en => tlb_plru_acc_en,
455 process(tlb_req_index, tlb_hit, tlb_hit_way, tlb_plru_out)
458 if tlb_hit = '1' and tlb_req_index = i then
459 tlb_plru_acc_en <= '1';
461 tlb_plru_acc_en <= '0';
463 tlb_plru_acc <= std_ulogic_vector(to_unsigned(tlb_hit_way, TLB_WAY_BITS));
464 tlb_plru_victim(i) <= tlb_plru_out;
469 tlb_search : process(all)
470 variable hitway : tlb_way_t;
471 variable hit : std_ulogic;
472 variable eatag : tlb_tag_t;
474 tlb_req_index <= to_integer(unsigned(r0.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1
475 downto TLB_LG_PGSZ)));
478 eatag := r0.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
479 for i in tlb_way_t loop
480 if tlb_valid_way(i) = '1' and
481 read_tlb_tag(i, tlb_tag_way) = eatag then
486 tlb_hit <= hit and r0_valid;
487 tlb_hit_way <= hitway;
488 pte <= read_tlb_pte(hitway, tlb_pte_way);
489 valid_ra <= tlb_hit or not r0.virt_mode;
490 if r0.virt_mode = '1' then
491 ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
492 r0.addr(TLB_LG_PGSZ - 1 downto 0);
494 ra <= r0.addr(REAL_ADDR_BITS - 1 downto 0);
498 tlb_update : process(clk)
499 variable tlbie : std_ulogic;
500 variable tlbia : std_ulogic;
501 variable tlbwe : std_ulogic;
502 variable repl_way : tlb_way_t;
503 variable eatag : tlb_tag_t;
504 variable tagset : tlb_way_tags_t;
505 variable pteset : tlb_way_ptes_t;
507 if rising_edge(clk) then
511 if r0_valid = '1' and r0.tlbie = '1' then
512 if r0.addr(11 downto 10) /= "00" then
514 elsif r0.addr(9) = '1' then
520 if rst = '1' or tlbia = '1' then
521 -- clear all valid bits at once
522 for i in tlb_index_t loop
523 dtlb_valids(i) <= (others => '0');
525 elsif tlbie = '1' then
526 if tlb_hit = '1' then
527 dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
529 elsif tlbwe = '1' then
530 if tlb_hit = '1' then
531 repl_way := tlb_hit_way;
533 repl_way := to_integer(unsigned(tlb_plru_victim(tlb_req_index)));
535 eatag := r0.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
536 tagset := tlb_tag_way;
537 write_tlb_tag(repl_way, tagset, eatag);
538 dtlb_tags(tlb_req_index) <= tagset;
539 pteset := tlb_pte_way;
540 write_tlb_pte(repl_way, pteset, r0.data);
541 dtlb_ptes(tlb_req_index) <= pteset;
542 dtlb_valids(tlb_req_index)(repl_way) <= '1';
548 maybe_plrus: if NUM_WAYS > 1 generate
550 plrus: for i in 0 to NUM_LINES-1 generate
552 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
553 signal plru_acc_en : std_ulogic;
554 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
557 plru : entity work.plru
565 acc_en => plru_acc_en,
569 process(req_index, req_op, req_hit_way, plru_out)
572 if (req_op = OP_LOAD_HIT or
573 req_op = OP_STORE_HIT) and req_index = i then
578 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
579 plru_victim(i) <= plru_out;
584 -- Cache request parsing and hit detection
585 dcache_request : process(all)
586 variable is_hit : std_ulogic;
587 variable hit_way : way_t;
589 variable opsel : std_ulogic_vector(2 downto 0);
590 variable go : std_ulogic;
591 variable s_hit : std_ulogic;
592 variable s_tag : cache_tag_t;
593 variable s_pte : tlb_pte_t;
594 variable s_ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
595 variable hit_set : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
596 variable hit_way_set : hit_way_set_t;
598 -- Extract line, row and tag from request
599 req_index <= get_index(r0.addr);
600 req_row <= get_row(r0.addr);
601 req_tag <= get_tag(ra);
603 -- Only do anything if not being stalled by stage 1
604 go := r0_valid and not r0.tlbie;
606 -- Calculate address of beginning of cache line, will be
607 -- used for cache miss processing if needed
609 req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
610 ra(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
611 (LINE_OFF_BITS-1 downto 0 => '0');
613 -- Test if pending request is a hit on any way
614 -- In order to make timing in virtual mode, when we are using the TLB,
615 -- we compare each way with each of the real addresses from each way of
616 -- the TLB, and then decide later which match to use.
619 if r0.virt_mode = '1' then
620 for j in tlb_way_t loop
623 s_pte := read_tlb_pte(j, tlb_pte_way);
624 s_ra := s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
625 r0.addr(TLB_LG_PGSZ - 1 downto 0);
626 s_tag := get_tag(s_ra);
628 if go = '1' and cache_valids(req_index)(i) = '1' and
629 read_tag(i, cache_tags(req_index)) = s_tag and
630 tlb_valid_way(j) = '1' then
637 if tlb_hit = '1' then
638 is_hit := hit_set(tlb_hit_way);
639 hit_way := hit_way_set(tlb_hit_way);
642 s_tag := get_tag(r0.addr(REAL_ADDR_BITS - 1 downto 0));
644 if go = '1' and cache_valids(req_index)(i) = '1' and
645 read_tag(i, cache_tags(req_index)) = s_tag then
652 -- The way that matched on a hit
653 req_hit_way <= hit_way;
655 -- The way to replace on a miss
656 replace_way <= to_integer(unsigned(plru_victim(req_index)));
658 -- Combine the request and cache his status to decide what
659 -- operation needs to be done
663 if valid_ra = '1' then
664 opsel := r0.load & r0.nc & is_hit;
666 when "101" => op := OP_LOAD_HIT;
667 when "100" => op := OP_LOAD_MISS;
668 when "110" => op := OP_LOAD_NC;
669 when "001" => op := OP_STORE_HIT;
670 when "000" => op := OP_STORE_MISS;
671 when "010" => op := OP_STORE_MISS;
672 when "011" => op := OP_BAD;
673 when "111" => op := OP_BAD;
674 when others => op := OP_NONE;
682 -- Version of the row number that is valid one cycle earlier
683 -- in the cases where we need to read the cache data BRAM.
684 -- If we're stalling then we need to keep reading the last
686 if stall_out = '0' then
687 early_req_row <= get_row(d_in.addr);
689 early_req_row <= req_row;
693 -- Wire up wishbone request latch out of stage 1
694 wishbone_out <= r1.wb;
696 -- Generate stalls from stage 1 state machine
697 stall_out <= '1' when r1.state /= IDLE else '0';
699 -- Handle load-with-reservation and store-conditional instructions
700 reservation_comb: process(all)
705 if r0_valid = '1' and r0.reserve = '1' then
706 -- XXX generate alignment interrupt if address is not aligned
707 -- XXX or if r0.nc = '1'
708 if r0.load = '1' then
709 -- load with reservation
714 if reservation.valid = '0' or
715 r0.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
722 reservation_reg: process(clk)
724 if rising_edge(clk) then
725 if rst = '1' or clear_rsrv = '1' then
726 reservation.valid <= '0';
727 elsif set_rsrv = '1' then
728 reservation.valid <= '1';
729 reservation.addr <= r0.addr(63 downto LINE_OFF_BITS);
734 -- Return data for loads & completion control logic
736 writeback_control: process(all)
739 -- The mux on d_out.data defaults to the normal load hit case.
741 d_out.data <= cache_out(r1.hit_way);
742 d_out.store_done <= '0';
744 d_out.tlb_miss <= '0';
746 -- We have a valid load or store hit or we just completed a slow
747 -- op such as a load miss, a NC load or a store
749 -- Note: the load hit is delayed by one cycle. However it can still
750 -- not collide with r.slow_valid (well unless I miscalculated) because
751 -- slow_valid can only be set on a subsequent request and not on its
752 -- first cycle (the state machine must have advanced), which makes
753 -- slow_valid at least 2 cycles from the previous hit_load_valid.
756 -- Sanity: Only one of these must be set in any given cycle
757 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
758 "unexpected slow_valid collision with stcx_fail"
760 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
761 "unexpected hit_load_delayed collision with slow_valid"
764 -- Load hit case is the standard path
765 if r1.hit_load_valid = '1' then
766 report "completing load hit";
770 -- error cases complete without stalling
771 if r1.error_done = '1' then
772 report "completing ld/st with error";
774 d_out.tlb_miss <= r1.tlb_miss;
778 -- tlbie is handled above and doesn't go through the cache state machine
779 if r1.tlbie_done = '1' then
780 report "completing tlbie";
784 -- Slow ops (load miss, NC, stores)
785 if r1.slow_valid = '1' then
786 -- If it's a load, enable register writeback and switch
790 -- Read data comes from the slow data latch
791 d_out.data <= r1.slow_data;
793 d_out.store_done <= '1';
795 report "completing store or load miss";
799 if r1.stcx_fail = '1' then
800 d_out.store_done <= '0';
807 -- Generate a cache RAM for each way. This handles the normal
808 -- reads, writes from reloads and the special store-hit update
811 -- Note: the BRAMs have an extra read buffer, meaning the output
812 -- is pipelined an extra cycle. This differs from the
813 -- icache. The writeback logic needs to take that into
814 -- account by using 1-cycle delayed signals for load hits.
816 rams: for i in 0 to NUM_WAYS-1 generate
817 signal do_read : std_ulogic;
818 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
819 signal do_write : std_ulogic;
820 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
821 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
822 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
823 signal dout : cache_row_t;
825 way: entity work.cache_ram
827 ROW_BITS => ROW_BITS,
828 WIDTH => wishbone_data_bits,
842 variable tmp_adr : std_ulogic_vector(63 downto 0);
843 variable reloading : boolean;
847 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
848 cache_out(i) <= dout;
852 -- Defaults to wishbone read responses (cache refill),
854 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
855 -- other than the current state. Only the do_write signal is.
857 if r1.state = IDLE then
858 -- In IDLE state, the only write path is the store-hit update case
859 wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
861 wr_sel <= r0.byte_sel;
863 -- Otherwise, we might be doing a reload or a DCBZ
864 if r1.req.dcbz = '1' then
865 wr_data <= (others => '0');
867 wr_data <= wishbone_in.dat;
869 wr_sel <= (others => '1');
870 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
873 -- The two actual write cases here
875 reloading := r1.state = RELOAD_WAIT_ACK;
876 if reloading and wishbone_in.ack = '1' and r1.store_way = i then
879 if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' and
880 r1.req.dcbz = '0' then
881 assert not reloading report "Store hit while in state:" &
882 state_t'image(r1.state)
890 -- Cache hit synchronous machine for the easy case. This handles load hits.
891 -- It also handles error cases (TLB miss, cache paradox)
893 dcache_fast_hit : process(clk)
895 if rising_edge(clk) then
896 -- If we have a request incoming, we have to latch it as r0.valid
897 -- is only set for a single cycle. It's up to the control logic to
898 -- ensure we don't override an uncompleted request (for now we are
899 -- single issue on load/stores so we are fine, later, we can generate
900 -- a stall output if necessary).
902 if req_op /= OP_NONE and stall_out = '0' then
904 report "op:" & op_t'image(req_op) &
905 " addr:" & to_hstring(r0.addr) &
906 " nc:" & std_ulogic'image(r0.nc) &
907 " idx:" & integer'image(req_index) &
908 " tag:" & to_hstring(req_tag) &
909 " way: " & integer'image(req_hit_way);
912 -- Fast path for load/store hits. Set signals for the writeback controls.
913 if req_op = OP_LOAD_HIT then
914 r1.hit_way <= req_hit_way;
915 r1.hit_load_valid <= '1';
917 r1.hit_load_valid <= '0';
920 if req_op = OP_BAD then
921 r1.error_done <= '1';
922 r1.tlb_miss <= not valid_ra;
924 r1.error_done <= '0';
927 -- complete tlbies in the third cycle
928 r1.tlbie_done <= r0_valid and r0.tlbie;
933 -- Every other case is handled by this state machine:
935 -- * Cache load miss/reload (in conjunction with "rams")
936 -- * Load hits for non-cachable forms
937 -- * Stores (the collision case is handled in "rams")
939 -- All wishbone requests generation is done here. This machine
940 -- operates at stage 1.
942 dcache_slow : process(clk)
943 variable tagset : cache_tags_set_t;
944 variable stbs_done : boolean;
946 if rising_edge(clk) then
947 -- On reset, clear all valid bits to force misses
949 for i in index_t loop
950 cache_valids(i) <= (others => '0');
953 r1.slow_valid <= '0';
957 -- Not useful normally but helps avoiding tons of sim warnings
958 r1.wb.adr <= (others => '0');
960 -- One cycle pulses reset
961 r1.slow_valid <= '0';
964 -- Main state machine
969 -- stay in IDLE state
972 -- Normal load cache miss, start the reload machine
974 report "cache miss addr:" & to_hstring(r0.addr) &
975 " idx:" & integer'image(req_index) &
976 " way:" & integer'image(replace_way) &
977 " tag:" & to_hstring(req_tag);
979 -- Force misses on that way while reloading that line
980 cache_valids(req_index)(replace_way) <= '0';
982 -- Store new tag in selected way
983 for i in 0 to NUM_WAYS-1 loop
984 if i = replace_way then
985 tagset := cache_tags(req_index);
986 write_tag(i, tagset, req_tag);
987 cache_tags(req_index) <= tagset;
991 -- Keep track of our index and way for subsequent stores.
992 r1.store_index <= req_index;
993 r1.store_way <= replace_way;
994 r1.store_row <= get_row(req_laddr);
996 -- Prep for first wishbone read. We calculate the address of
997 -- the start of the cache line and start the WB cycle
999 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
1000 r1.wb.sel <= (others => '1');
1005 -- Track that we had one request sent
1006 r1.state <= RELOAD_WAIT_ACK;
1009 r1.wb.sel <= r0.byte_sel;
1010 r1.wb.adr <= ra(r1.wb.adr'left downto 3) & "000";
1014 r1.state <= NC_LOAD_WAIT_ACK;
1016 when OP_STORE_HIT | OP_STORE_MISS =>
1017 if r0.dcbz = '0' then
1018 r1.wb.sel <= r0.byte_sel;
1019 r1.wb.adr <= ra(r1.wb.adr'left downto 3) & "000";
1020 r1.wb.dat <= r0.data;
1021 if cancel_store = '0' then
1025 r1.state <= STORE_WAIT_ACK;
1027 r1.stcx_fail <= '1';
1031 -- dcbz is handled much like a load miss except
1032 -- that we are writing to memory instead of reading
1033 r1.store_index <= req_index;
1034 r1.store_row <= get_row(req_laddr);
1036 if req_op = OP_STORE_HIT then
1037 r1.store_way <= req_hit_way;
1039 r1.store_way <= replace_way;
1041 -- Force misses on the victim way while zeroing
1042 cache_valids(req_index)(replace_way) <= '0';
1044 -- Store new tag in selected way
1045 for i in 0 to NUM_WAYS-1 loop
1046 if i = replace_way then
1047 tagset := cache_tags(req_index);
1048 write_tag(i, tagset, req_tag);
1049 cache_tags(req_index) <= tagset;
1054 -- Set up for wishbone writes
1055 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
1056 r1.wb.sel <= (others => '1');
1058 r1.wb.dat <= (others => '0');
1062 -- Handle the rest like a load miss
1063 r1.state <= RELOAD_WAIT_ACK;
1066 -- OP_NONE and OP_BAD do nothing
1067 -- OP_BAD was handled above already
1072 when RELOAD_WAIT_ACK =>
1073 -- Requests are all sent if stb is 0
1074 stbs_done := r1.wb.stb = '0';
1076 -- If we are still sending requests, was one accepted ?
1077 if wishbone_in.stall = '0' and not stbs_done then
1078 -- That was the last word ? We are done sending. Clear
1079 -- stb and set stbs_done so we can handle an eventual last
1080 -- ack on the same cycle.
1082 if is_last_row_addr(r1.wb.adr) then
1087 -- Calculate the next row address
1088 r1.wb.adr <= next_row_addr(r1.wb.adr);
1091 -- Incoming acks processing
1092 if wishbone_in.ack = '1' then
1093 -- Is this the data we were looking for ? Latch it so
1094 -- we can respond later. We don't currently complete the
1095 -- pending miss request immediately, we wait for the
1096 -- whole line to be loaded. The reason is that if we
1097 -- did, we would potentially get new requests in while
1098 -- not idle, which we don't currently know how to deal
1101 if r1.store_row = get_row(r1.req.addr) and r1.req.dcbz = '0' then
1102 r1.slow_data <= wishbone_in.dat;
1105 -- Check for completion
1106 if stbs_done and is_last_row(r1.store_row) then
1107 -- Complete wishbone cycle
1110 -- Cache line is now valid
1111 cache_valids(r1.store_index)(r1.store_way) <= '1';
1113 -- Don't complete and go idle until next cycle, in
1114 -- case the next request is for the last dword of
1115 -- the cache line we just loaded.
1116 r1.state <= FINISH_LD_MISS;
1119 -- Increment store row counter
1120 r1.store_row <= next_row(r1.store_row);
1123 when FINISH_LD_MISS =>
1124 -- Write back the load data that we got
1125 r1.slow_valid <= '1';
1127 report "completing miss !";
1129 when STORE_WAIT_ACK | NC_LOAD_WAIT_ACK =>
1130 -- Clear stb when slave accepted request
1131 if wishbone_in.stall = '0' then
1135 -- Got ack ? complete.
1136 if wishbone_in.ack = '1' then
1137 if r1.state = NC_LOAD_WAIT_ACK then
1138 r1.slow_data <= wishbone_in.dat;
1141 r1.slow_valid <= '1';