2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
19 use work.wishbone_types.all;
24 LINE_SIZE : positive := 64;
25 -- Number of lines in a set
26 NUM_LINES : positive := 32;
28 NUM_WAYS : positive := 4;
29 -- L1 DTLB entries per set
30 TLB_SET_SIZE : positive := 64;
31 -- L1 DTLB number of sets
32 TLB_NUM_WAYS : positive := 2;
33 -- L1 DTLB log_2(page_size)
34 TLB_LG_PGSZ : positive := 12;
35 -- Non-zero to enable log data collection
36 LOG_LENGTH : natural := 0
42 d_in : in Loadstore1ToDcacheType;
43 d_out : out DcacheToLoadstore1Type;
45 m_in : in MmuToDcacheType;
46 m_out : out DcacheToMmuType;
48 stall_out : out std_ulogic;
50 wishbone_out : out wishbone_master_out;
51 wishbone_in : in wishbone_slave_out;
53 log_out : out std_ulogic_vector(19 downto 0)
57 architecture rtl of dcache is
58 -- BRAM organisation: We never access more than wishbone_data_bits at
59 -- a time so to save resources we make the array only that wide, and
60 -- use consecutive indices for to make a cache "line"
62 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
63 constant ROW_SIZE : natural := wishbone_data_bits / 8;
64 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
65 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
66 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
68 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
70 -- Bit fields counts in the address
72 -- REAL_ADDR_BITS is the number of real address bits that we store
73 constant REAL_ADDR_BITS : positive := 56;
74 -- ROW_BITS is the number of bits to select a row
75 constant ROW_BITS : natural := log2(BRAM_ROWS);
76 -- ROW_LINEBITS is the number of bits to select a row within a line
77 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
78 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
79 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
80 -- ROW_OFF_BITS is the number of bits for the offset in a row
81 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
82 -- INDEX_BITS is the number if bits to select a cache line
83 constant INDEX_BITS : natural := log2(NUM_LINES);
84 -- SET_SIZE_BITS is the log base 2 of the set size
85 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
86 -- TAG_BITS is the number of bits of the tag part of the address
87 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
88 -- TAG_WIDTH is the width in bits of each way of the tag RAM
89 constant TAG_WIDTH : natural := TAG_BITS + 7 - ((TAG_BITS + 7) mod 8);
90 -- WAY_BITS is the number of bits to select a way
91 constant WAY_BITS : natural := log2(NUM_WAYS);
93 -- Example of layout for 32 lines of 64 bytes:
95 -- .. tag |index| line |
97 -- .. | |---| | ROW_LINEBITS (3)
98 -- .. | |--- - --| LINE_OFF_BITS (6)
99 -- .. | |- --| ROW_OFF_BITS (3)
100 -- .. |----- ---| | ROW_BITS (8)
101 -- .. |-----| | INDEX_BITS (5)
102 -- .. --------| | TAG_BITS (45)
104 subtype row_t is integer range 0 to BRAM_ROWS-1;
105 subtype index_t is integer range 0 to NUM_LINES-1;
106 subtype way_t is integer range 0 to NUM_WAYS-1;
107 subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
109 -- The cache data BRAM organized as described above for each way
110 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
112 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
113 -- not handle a clean (commented) definition of the cache tags as a 3d
114 -- memory. For now, work around it by putting all the tags
115 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
116 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
117 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
118 constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
119 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
120 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
122 -- The cache valid bits
123 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
124 type cache_valids_t is array(index_t) of cache_way_valids_t;
125 type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
127 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
128 signal cache_tags : cache_tags_array_t;
129 signal cache_tag_set : cache_tags_set_t;
130 signal cache_valids : cache_valids_t;
132 attribute ram_style : string;
133 attribute ram_style of cache_tags : signal is "distributed";
136 constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
137 constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
138 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
139 constant TLB_TAG_WAY_BITS : natural := TLB_NUM_WAYS * TLB_EA_TAG_BITS;
140 constant TLB_PTE_BITS : natural := 64;
141 constant TLB_PTE_WAY_BITS : natural := TLB_NUM_WAYS * TLB_PTE_BITS;
143 subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
144 subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
145 subtype tlb_way_valids_t is std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
146 type tlb_valids_t is array(tlb_index_t) of tlb_way_valids_t;
147 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
148 subtype tlb_way_tags_t is std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
149 type tlb_tags_t is array(tlb_index_t) of tlb_way_tags_t;
150 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
151 subtype tlb_way_ptes_t is std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
152 type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
153 type hit_way_set_t is array(tlb_way_t) of way_t;
155 signal dtlb_valids : tlb_valids_t;
156 signal dtlb_tags : tlb_tags_t;
157 signal dtlb_ptes : tlb_ptes_t;
158 attribute ram_style of dtlb_tags : signal is "distributed";
159 attribute ram_style of dtlb_ptes : signal is "distributed";
161 -- Record for storing permission, attribute, etc. bits from a PTE
162 type perm_attr_t is record
163 reference : std_ulogic;
164 changed : std_ulogic;
165 nocache : std_ulogic;
167 rd_perm : std_ulogic;
168 wr_perm : std_ulogic;
171 function extract_perm_attr(pte : std_ulogic_vector(TLB_PTE_BITS - 1 downto 0)) return perm_attr_t is
172 variable pa : perm_attr_t;
174 pa.reference := pte(8);
175 pa.changed := pte(7);
176 pa.nocache := pte(5);
178 pa.rd_perm := pte(2);
179 pa.wr_perm := pte(1);
183 constant real_mode_perm_attr : perm_attr_t := (nocache => '0', others => '1');
185 -- Type of operation on a "valid" input
186 type op_t is (OP_NONE,
187 OP_BAD, -- NC cache hit, TLB miss, prot/RC failure
188 OP_STCX_FAIL, -- conditional store w/o reservation
189 OP_LOAD_HIT, -- Cache hit on load
190 OP_LOAD_MISS, -- Load missing cache
191 OP_LOAD_NC, -- Non-cachable load
192 OP_STORE_HIT, -- Store hitting cache
193 OP_STORE_MISS); -- Store missing cache
195 -- Cache state machine
196 type state_t is (IDLE, -- Normal load hit processing
197 RELOAD_WAIT_ACK, -- Cache reload wait ack
198 STORE_WAIT_ACK, -- Store wait ack
199 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
203 -- Dcache operations:
205 -- In order to make timing, we use the BRAMs with an output buffer,
206 -- which means that the BRAM output is delayed by an extra cycle.
208 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
211 -- All other operations are handled via stalling in the first stage.
213 -- The second stage can thus complete a hit at the same time as the
214 -- first stage emits a stall for a complex op.
217 -- Stage 0 register, basically contains just the latched request
218 type reg_stage_0_t is record
219 req : Loadstore1ToDcacheType;
223 mmu_req : std_ulogic; -- indicates source of request
226 signal r0 : reg_stage_0_t;
227 signal r0_full : std_ulogic;
229 type mem_access_request_t is record
233 real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
234 data : std_ulogic_vector(63 downto 0);
235 byte_sel : std_ulogic_vector(7 downto 0);
237 same_tag : std_ulogic;
240 -- First stage register, contains state for stage 1 of load hits
241 -- and for the state machine used by all other operations
243 type reg_stage_1_t is record
244 -- Info about the request
245 full : std_ulogic; -- have uncompleted request
246 mmu_req : std_ulogic; -- request is from MMU
247 req : mem_access_request_t;
251 hit_load_valid : std_ulogic;
253 cache_hit : std_ulogic;
256 tlb_hit : std_ulogic;
257 tlb_hit_way : tlb_way_t;
258 tlb_hit_index : tlb_index_t;
260 -- 2-stage data buffer for data forwarded from writes to reads
261 forward_data1 : std_ulogic_vector(63 downto 0);
262 forward_data2 : std_ulogic_vector(63 downto 0);
263 forward_sel1 : std_ulogic_vector(7 downto 0);
264 forward_valid1 : std_ulogic;
265 forward_way1 : way_t;
266 forward_row1 : row_t;
267 use_forward1 : std_ulogic;
268 forward_sel : std_ulogic_vector(7 downto 0);
270 -- Cache miss state (reload state machine)
273 write_bram : std_ulogic;
274 write_tag : std_ulogic;
275 slow_valid : std_ulogic;
276 wb : wishbone_master_out;
277 reload_tag : cache_tag_t;
280 store_index : index_t;
281 end_row_ix : row_in_line_t;
282 rows_valid : row_per_line_valid_t;
283 acks_pending : unsigned(2 downto 0);
285 -- Signals to complete with error
286 error_done : std_ulogic;
287 cache_paradox : std_ulogic;
289 -- Signal to complete a failed stcx.
290 stcx_fail : std_ulogic;
292 -- completion signal for tlbie
293 tlbie_done : std_ulogic;
296 signal r1 : reg_stage_1_t;
298 -- Reservation information
300 type reservation_t is record
302 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
305 signal reservation : reservation_t;
307 -- Async signals on incoming request
308 signal req_index : index_t;
309 signal req_row : row_t;
310 signal req_hit_way : way_t;
311 signal req_tag : cache_tag_t;
312 signal req_op : op_t;
313 signal req_data : std_ulogic_vector(63 downto 0);
314 signal req_same_tag : std_ulogic;
315 signal req_go : std_ulogic;
317 signal early_req_row : row_t;
319 signal cancel_store : std_ulogic;
320 signal set_rsrv : std_ulogic;
321 signal clear_rsrv : std_ulogic;
323 signal r0_valid : std_ulogic;
324 signal r0_stall : std_ulogic;
326 signal use_forward1_next : std_ulogic;
327 signal use_forward2_next : std_ulogic;
329 -- Cache RAM interface
330 type cache_ram_out_t is array(way_t) of cache_row_t;
331 signal cache_out : cache_ram_out_t;
333 -- PLRU output interface
334 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
335 signal plru_victim : plru_out_t;
336 signal replace_way : way_t;
338 -- Wishbone read/write/cache write formatting signals
339 signal bus_sel : std_ulogic_vector(7 downto 0);
342 signal tlb_tag_way : tlb_way_tags_t;
343 signal tlb_pte_way : tlb_way_ptes_t;
344 signal tlb_valid_way : tlb_way_valids_t;
345 signal tlb_req_index : tlb_index_t;
346 signal tlb_hit : std_ulogic;
347 signal tlb_hit_way : tlb_way_t;
348 signal pte : tlb_pte_t;
349 signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
350 signal valid_ra : std_ulogic;
351 signal perm_attr : perm_attr_t;
352 signal rc_ok : std_ulogic;
353 signal perm_ok : std_ulogic;
354 signal access_ok : std_ulogic;
356 -- TLB PLRU output interface
357 type tlb_plru_out_t is array(tlb_index_t) of std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
358 signal tlb_plru_victim : tlb_plru_out_t;
361 -- Helper functions to decode incoming requests
364 -- Return the cache line index (tag index) for an address
365 function get_index(addr: std_ulogic_vector) return index_t is
367 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
370 -- Return the cache row index (data memory) for an address
371 function get_row(addr: std_ulogic_vector) return row_t is
373 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
376 -- Return the index of a row within a line
377 function get_row_of_line(row: row_t) return row_in_line_t is
378 variable row_v : unsigned(ROW_BITS-1 downto 0);
380 row_v := to_unsigned(row, ROW_BITS);
381 return row_v(ROW_LINEBITS-1 downto 0);
384 -- Returns whether this is the last row of a line
385 function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
387 return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
390 -- Returns whether this is the last row of a line
391 function is_last_row(row: row_t; last: row_in_line_t) return boolean is
393 return get_row_of_line(row) = last;
396 -- Return the address of the next row in the current cache line
397 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
398 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
399 variable result : wishbone_addr_type;
401 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
402 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
403 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
405 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
409 -- Return the next row in the current cache line. We use a dedicated
410 -- function in order to limit the size of the generated adder to be
411 -- only the bits within a cache line (3 bits with default settings)
413 function next_row(row: row_t) return row_t is
414 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
415 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
416 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
418 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
419 row_idx := row_v(ROW_LINEBITS-1 downto 0);
420 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
421 return to_integer(unsigned(row_v));
424 -- Get the tag value from the address
425 function get_tag(addr: std_ulogic_vector) return cache_tag_t is
427 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
430 -- Read a tag from a tag memory row
431 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
433 return tagset(way * TAG_WIDTH + TAG_BITS - 1 downto way * TAG_WIDTH);
436 -- Read a TLB tag from a TLB tag memory row
437 function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is
438 variable j : integer;
440 j := way * TLB_EA_TAG_BITS;
441 return tags(j + TLB_EA_TAG_BITS - 1 downto j);
444 -- Write a TLB tag to a TLB tag memory row
445 procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
447 variable j : integer;
449 j := way * TLB_EA_TAG_BITS;
450 tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
453 -- Read a PTE from a TLB PTE memory row
454 function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is
455 variable j : integer;
457 j := way * TLB_PTE_BITS;
458 return ptes(j + TLB_PTE_BITS - 1 downto j);
461 procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
462 variable j : integer;
464 j := way * TLB_PTE_BITS;
465 ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
470 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
471 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
472 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
473 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
474 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
475 report "geometry bits don't add up" severity FAILURE;
476 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
477 report "geometry bits don't add up" severity FAILURE;
478 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
479 report "geometry bits don't add up" severity FAILURE;
480 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
481 report "geometry bits don't add up" severity FAILURE;
482 assert (64 = wishbone_data_bits)
483 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
484 assert SET_SIZE_BITS <= TLB_LG_PGSZ report "Set indexed by virtual address" severity FAILURE;
486 -- Latch the request in r0.req as long as we're not stalling
487 stage_0 : process(clk)
488 variable r : reg_stage_0_t;
490 if rising_edge(clk) then
491 assert (d_in.valid and m_in.valid) = '0' report
492 "request collision loadstore vs MMU";
493 if m_in.valid = '1' then
495 r.req.load := not (m_in.tlbie or m_in.tlbld);
498 r.req.reserve := '0';
499 r.req.virt_mode := '0';
500 r.req.priv_mode := '1';
501 r.req.addr := m_in.addr;
502 r.req.data := m_in.pte;
503 r.req.byte_sel := (others => '1');
504 r.tlbie := m_in.tlbie;
505 r.doall := m_in.doall;
506 r.tlbld := m_in.tlbld;
517 elsif r1.full = '0' or r0_full = '0' then
519 r0_full <= r.req.valid;
524 -- we don't yet handle collisions between loadstore1 requests and MMU requests
527 -- Hold off the request in r0 when r1 has an uncompleted request
528 r0_stall <= r0_full and r1.full;
529 r0_valid <= r0_full and not r1.full;
530 stall_out <= r0_stall;
533 -- Operates in the second cycle on the request latched in r0.req.
534 -- TLB updates write the entry at the end of the second cycle.
535 tlb_read : process(clk)
536 variable index : tlb_index_t;
537 variable addrbits : std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
539 if rising_edge(clk) then
540 if m_in.valid = '1' then
541 addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
543 addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ);
545 index := to_integer(unsigned(addrbits));
546 -- If we have any op and the previous op isn't finished,
547 -- then keep the same output for next cycle.
548 if r0_stall = '0' then
549 tlb_valid_way <= dtlb_valids(index);
550 tlb_tag_way <= dtlb_tags(index);
551 tlb_pte_way <= dtlb_ptes(index);
556 -- Generate TLB PLRUs
557 maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
559 tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
560 -- TLB PLRU interface
561 signal tlb_plru_acc : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
562 signal tlb_plru_acc_en : std_ulogic;
563 signal tlb_plru_out : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
565 tlb_plru : entity work.plru
573 acc_en => tlb_plru_acc_en,
580 if r1.tlb_hit_index = i then
581 tlb_plru_acc_en <= r1.tlb_hit;
583 tlb_plru_acc_en <= '0';
585 tlb_plru_acc <= std_ulogic_vector(to_unsigned(r1.tlb_hit_way, TLB_WAY_BITS));
586 tlb_plru_victim(i) <= tlb_plru_out;
591 tlb_search : process(all)
592 variable hitway : tlb_way_t;
593 variable hit : std_ulogic;
594 variable eatag : tlb_tag_t;
596 tlb_req_index <= to_integer(unsigned(r0.req.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1
597 downto TLB_LG_PGSZ)));
600 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
601 for i in tlb_way_t loop
602 if tlb_valid_way(i) = '1' and
603 read_tlb_tag(i, tlb_tag_way) = eatag then
608 tlb_hit <= hit and r0_valid;
609 tlb_hit_way <= hitway;
610 if tlb_hit = '1' then
611 pte <= read_tlb_pte(hitway, tlb_pte_way);
613 pte <= (others => '0');
615 valid_ra <= tlb_hit or not r0.req.virt_mode;
616 if r0.req.virt_mode = '1' then
617 ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
618 r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
619 (ROW_OFF_BITS-1 downto 0 => '0');
620 perm_attr <= extract_perm_attr(pte);
622 ra <= r0.req.addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
623 (ROW_OFF_BITS-1 downto 0 => '0');
624 perm_attr <= real_mode_perm_attr;
628 tlb_update : process(clk)
629 variable tlbie : std_ulogic;
630 variable tlbwe : std_ulogic;
631 variable repl_way : tlb_way_t;
632 variable eatag : tlb_tag_t;
633 variable tagset : tlb_way_tags_t;
634 variable pteset : tlb_way_ptes_t;
636 if rising_edge(clk) then
637 tlbie := r0_valid and r0.tlbie;
638 tlbwe := r0_valid and r0.tlbld;
639 if rst = '1' or (tlbie = '1' and r0.doall = '1') then
640 -- clear all valid bits at once
641 for i in tlb_index_t loop
642 dtlb_valids(i) <= (others => '0');
644 elsif tlbie = '1' then
645 if tlb_hit = '1' then
646 dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
648 elsif tlbwe = '1' then
649 if tlb_hit = '1' then
650 repl_way := tlb_hit_way;
652 repl_way := to_integer(unsigned(tlb_plru_victim(tlb_req_index)));
654 eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
655 tagset := tlb_tag_way;
656 write_tlb_tag(repl_way, tagset, eatag);
657 dtlb_tags(tlb_req_index) <= tagset;
658 pteset := tlb_pte_way;
659 write_tlb_pte(repl_way, pteset, r0.req.data);
660 dtlb_ptes(tlb_req_index) <= pteset;
661 dtlb_valids(tlb_req_index)(repl_way) <= '1';
667 maybe_plrus: if NUM_WAYS > 1 generate
669 plrus: for i in 0 to NUM_LINES-1 generate
671 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
672 signal plru_acc_en : std_ulogic;
673 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
676 plru : entity work.plru
684 acc_en => plru_acc_en,
691 if r1.hit_index = i then
692 plru_acc_en <= r1.cache_hit;
696 plru_acc <= std_ulogic_vector(to_unsigned(r1.hit_way, WAY_BITS));
697 plru_victim(i) <= plru_out;
702 -- Cache tag RAM read port
703 cache_tag_read : process(clk)
704 variable index : index_t;
706 if rising_edge(clk) then
707 if r0_stall = '1' then
709 elsif m_in.valid = '1' then
710 index := get_index(m_in.addr);
712 index := get_index(d_in.addr);
714 cache_tag_set <= cache_tags(index);
718 -- Cache request parsing and hit detection
719 dcache_request : process(all)
720 variable is_hit : std_ulogic;
721 variable hit_way : way_t;
723 variable opsel : std_ulogic_vector(2 downto 0);
724 variable go : std_ulogic;
725 variable nc : std_ulogic;
726 variable s_hit : std_ulogic;
727 variable s_tag : cache_tag_t;
728 variable s_pte : tlb_pte_t;
729 variable s_ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
730 variable hit_set : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
731 variable hit_way_set : hit_way_set_t;
732 variable rel_matches : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0);
733 variable rel_match : std_ulogic;
735 -- Extract line, row and tag from request
736 req_index <= get_index(r0.req.addr);
737 req_row <= get_row(r0.req.addr);
738 req_tag <= get_tag(ra);
740 go := r0_valid and not (r0.tlbie or r0.tlbld) and not r1.error_done;
742 -- Test if pending request is a hit on any way
743 -- In order to make timing in virtual mode, when we are using the TLB,
744 -- we compare each way with each of the real addresses from each way of
745 -- the TLB, and then decide later which match to use.
749 if r0.req.virt_mode = '1' then
750 rel_matches := (others => '0');
751 for j in tlb_way_t loop
754 s_pte := read_tlb_pte(j, tlb_pte_way);
755 s_ra := s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
756 r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
757 s_tag := get_tag(s_ra);
759 if go = '1' and cache_valids(req_index)(i) = '1' and
760 read_tag(i, cache_tag_set) = s_tag and
761 tlb_valid_way(j) = '1' then
767 if s_tag = r1.reload_tag then
768 rel_matches(j) := '1';
771 if tlb_hit = '1' then
772 is_hit := hit_set(tlb_hit_way);
773 hit_way := hit_way_set(tlb_hit_way);
774 rel_match := rel_matches(tlb_hit_way);
777 s_tag := get_tag(r0.req.addr);
779 if go = '1' and cache_valids(req_index)(i) = '1' and
780 read_tag(i, cache_tag_set) = s_tag then
785 if s_tag = r1.reload_tag then
789 req_same_tag <= rel_match;
791 -- See if the request matches the line currently being reloaded
792 if r1.state = RELOAD_WAIT_ACK and req_index = r1.store_index and
794 -- For a store, consider this a hit even if the row isn't valid
795 -- since it will be by the time we perform the store.
796 -- For a load, check the appropriate row valid bit.
797 is_hit := not r0.req.load or r1.rows_valid(req_row mod ROW_PER_LINE);
798 hit_way := replace_way;
801 -- Whether to use forwarded data for a load or not
802 use_forward1_next <= '0';
803 if get_row(r1.req.real_addr) = req_row and r1.req.hit_way = hit_way then
804 -- Only need to consider r1.write_bram here, since if we are
805 -- writing refill data here, then we don't have a cache hit this
806 -- cycle on the line being refilled. (There is the possibility
807 -- that the load following the load miss that started the refill
808 -- could be to the old contents of the victim line, since it is a
809 -- couple of cycles after the refill starts before we see the
810 -- updated cache tag. In that case we don't use the bypass.)
811 use_forward1_next <= r1.write_bram;
813 use_forward2_next <= '0';
814 if r1.forward_row1 = req_row and r1.forward_way1 = hit_way then
815 use_forward2_next <= r1.forward_valid1;
818 -- The way that matched on a hit
819 req_hit_way <= hit_way;
821 -- The way to replace on a miss
822 if r1.write_tag = '1' then
823 replace_way <= to_integer(unsigned(plru_victim(r1.store_index)));
825 replace_way <= r1.store_way;
828 -- work out whether we have permission for this access
829 -- NB we don't yet implement AMR, thus no KUAP
830 rc_ok <= perm_attr.reference and (r0.req.load or perm_attr.changed);
831 perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
832 (perm_attr.wr_perm or (r0.req.load and perm_attr.rd_perm));
833 access_ok <= valid_ra and perm_ok and rc_ok;
835 -- Combine the request and cache hit status to decide what
836 -- operation needs to be done
838 nc := r0.req.nc or perm_attr.nocache;
841 if access_ok = '0' then
843 elsif cancel_store = '1' then
846 opsel := r0.req.load & nc & is_hit;
848 when "101" => op := OP_LOAD_HIT;
849 when "100" => op := OP_LOAD_MISS;
850 when "110" => op := OP_LOAD_NC;
851 when "001" => op := OP_STORE_HIT;
852 when "000" => op := OP_STORE_MISS;
853 when "010" => op := OP_STORE_MISS;
854 when "011" => op := OP_BAD;
855 when "111" => op := OP_BAD;
856 when others => op := OP_NONE;
863 -- Version of the row number that is valid one cycle earlier
864 -- in the cases where we need to read the cache data BRAM.
865 -- If we're stalling then we need to keep reading the last
867 if r0_stall = '0' then
868 if m_in.valid = '1' then
869 early_req_row <= get_row(m_in.addr);
871 early_req_row <= get_row(d_in.addr);
874 early_req_row <= req_row;
878 -- Wire up wishbone request latch out of stage 1
879 wishbone_out <= r1.wb;
881 -- Handle load-with-reservation and store-conditional instructions
882 reservation_comb: process(all)
887 if r0_valid = '1' and r0.req.reserve = '1' then
888 -- XXX generate alignment interrupt if address is not aligned
889 -- XXX or if r0.req.nc = '1'
890 if r0.req.load = '1' then
891 -- load with reservation
896 if reservation.valid = '0' or
897 r0.req.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
904 reservation_reg: process(clk)
906 if rising_edge(clk) then
908 reservation.valid <= '0';
909 elsif r0_valid = '1' and access_ok = '1' then
910 if clear_rsrv = '1' then
911 reservation.valid <= '0';
912 elsif set_rsrv = '1' then
913 reservation.valid <= '1';
914 reservation.addr <= r0.req.addr(63 downto LINE_OFF_BITS);
920 -- Return data for loads & completion control logic
922 writeback_control: process(all)
923 variable data_out : std_ulogic_vector(63 downto 0);
924 variable data_fwd : std_ulogic_vector(63 downto 0);
925 variable j : integer;
927 -- Use the bypass if are reading the row that was written 1 or 2 cycles
928 -- ago, including for the slow_valid = 1 case (i.e. completing a load
929 -- miss or a non-cacheable load).
930 if r1.use_forward1 = '1' then
931 data_fwd := r1.forward_data1;
933 data_fwd := r1.forward_data2;
935 data_out := cache_out(r1.hit_way);
938 if r1.forward_sel(i) = '1' then
939 data_out(j + 7 downto j) := data_fwd(j + 7 downto j);
944 d_out.data <= data_out;
945 d_out.store_done <= '0';
947 d_out.cache_paradox <= '0';
950 m_out.done <= r1.tlbie_done;
952 m_out.data <= data_out;
954 -- We have a valid load or store hit or we just completed a slow
955 -- op such as a load miss, a NC load or a store
957 -- Note: the load hit is delayed by one cycle. However it can still
958 -- not collide with r.slow_valid (well unless I miscalculated) because
959 -- slow_valid can only be set on a subsequent request and not on its
960 -- first cycle (the state machine must have advanced), which makes
961 -- slow_valid at least 2 cycles from the previous hit_load_valid.
964 -- Sanity: Only one of these must be set in any given cycle
965 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
966 "unexpected slow_valid collision with stcx_fail"
968 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
969 "unexpected hit_load_delayed collision with slow_valid"
972 if r1.mmu_req = '0' then
973 -- Request came from loadstore1...
974 -- Load hit case is the standard path
975 if r1.hit_load_valid = '1' then
976 report "completing load hit data=" & to_hstring(data_out);
980 -- error cases complete without stalling
981 if r1.error_done = '1' then
982 report "completing ld/st with error";
984 d_out.cache_paradox <= r1.cache_paradox;
988 -- Slow ops (load miss, NC, stores)
989 if r1.slow_valid = '1' then
990 d_out.store_done <= '1';
991 report "completing store or load miss data=" & to_hstring(data_out);
995 if r1.stcx_fail = '1' then
996 d_out.store_done <= '0';
1001 -- Request came from MMU
1002 if r1.hit_load_valid = '1' then
1003 report "completing load hit to MMU, data=" & to_hstring(m_out.data);
1007 -- error cases complete without stalling
1008 if r1.error_done = '1' then
1009 report "completing MMU ld with error";
1014 -- Slow ops (i.e. load miss)
1015 if r1.slow_valid = '1' then
1016 report "completing MMU load miss, data=" & to_hstring(m_out.data);
1024 -- Generate a cache RAM for each way. This handles the normal
1025 -- reads, writes from reloads and the special store-hit update
1028 -- Note: the BRAMs have an extra read buffer, meaning the output
1029 -- is pipelined an extra cycle. This differs from the
1030 -- icache. The writeback logic needs to take that into
1031 -- account by using 1-cycle delayed signals for load hits.
1033 rams: for i in 0 to NUM_WAYS-1 generate
1034 signal do_read : std_ulogic;
1035 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1036 signal do_write : std_ulogic;
1037 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1038 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
1039 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
1040 signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
1041 signal dout : cache_row_t;
1043 way: entity work.cache_ram
1045 ROW_BITS => ROW_BITS,
1046 WIDTH => wishbone_data_bits,
1062 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
1063 cache_out(i) <= dout;
1067 -- Defaults to wishbone read responses (cache refill),
1069 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
1070 -- other than the current state.
1072 wr_sel_m <= (others => '0');
1075 if r1.write_bram = '1' then
1076 -- Write store data to BRAM. This happens one cycle after the
1078 wr_data <= r1.req.data;
1079 wr_sel <= r1.req.byte_sel;
1080 wr_addr <= std_ulogic_vector(to_unsigned(get_row(r1.req.real_addr), ROW_BITS));
1081 if i = r1.req.hit_way then
1085 -- Otherwise, we might be doing a reload or a DCBZ
1086 if r1.dcbz = '1' then
1087 wr_data <= (others => '0');
1089 wr_data <= wishbone_in.dat;
1091 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
1092 wr_sel <= (others => '1');
1094 if r1.state = RELOAD_WAIT_ACK and wishbone_in.ack = '1' and replace_way = i then
1099 -- Mask write selects with do_write since BRAM doesn't
1100 -- have a global write-enable
1101 if do_write = '1' then
1109 -- Cache hit synchronous machine for the easy case. This handles load hits.
1110 -- It also handles error cases (TLB miss, cache paradox)
1112 dcache_fast_hit : process(clk)
1114 if rising_edge(clk) then
1115 if req_op /= OP_NONE then
1116 report "op:" & op_t'image(req_op) &
1117 " addr:" & to_hstring(r0.req.addr) &
1118 " nc:" & std_ulogic'image(r0.req.nc) &
1119 " idx:" & integer'image(req_index) &
1120 " tag:" & to_hstring(req_tag) &
1121 " way: " & integer'image(req_hit_way);
1123 if r0_valid = '1' then
1124 r1.mmu_req <= r0.mmu_req;
1127 -- Fast path for load/store hits. Set signals for the writeback controls.
1128 r1.hit_way <= req_hit_way;
1129 r1.hit_index <= req_index;
1130 if req_op = OP_LOAD_HIT then
1131 r1.hit_load_valid <= '1';
1133 r1.hit_load_valid <= '0';
1135 if req_op = OP_LOAD_HIT or req_op = OP_STORE_HIT then
1136 r1.cache_hit <= '1';
1138 r1.cache_hit <= '0';
1141 if req_op = OP_BAD then
1142 report "Signalling ld/st error valid_ra=" & std_ulogic'image(valid_ra) &
1143 " rc_ok=" & std_ulogic'image(rc_ok) & " perm_ok=" & std_ulogic'image(perm_ok);
1144 r1.error_done <= '1';
1145 r1.cache_paradox <= access_ok;
1147 r1.error_done <= '0';
1148 r1.cache_paradox <= '0';
1151 if req_op = OP_STCX_FAIL then
1152 r1.stcx_fail <= '1';
1154 r1.stcx_fail <= '0';
1157 -- Record TLB hit information for updating TLB PLRU
1158 r1.tlb_hit <= tlb_hit;
1159 r1.tlb_hit_way <= tlb_hit_way;
1160 r1.tlb_hit_index <= tlb_req_index;
1162 -- complete tlbies and TLB loads in the third cycle
1163 r1.tlbie_done <= r0_valid and (r0.tlbie or r0.tlbld);
1168 -- Memory accesses are handled by this state machine:
1170 -- * Cache load miss/reload (in conjunction with "rams")
1171 -- * Load hits for non-cachable forms
1172 -- * Stores (the collision case is handled in "rams")
1174 -- All wishbone requests generation is done here. This machine
1175 -- operates at stage 1.
1177 dcache_slow : process(clk)
1178 variable stbs_done : boolean;
1179 variable req : mem_access_request_t;
1180 variable acks : unsigned(2 downto 0);
1182 if rising_edge(clk) then
1183 r1.use_forward1 <= use_forward1_next;
1184 r1.forward_sel <= (others => '0');
1185 if use_forward1_next = '1' then
1186 r1.forward_sel <= r1.req.byte_sel;
1187 elsif use_forward2_next = '1' then
1188 r1.forward_sel <= r1.forward_sel1;
1191 r1.forward_data2 <= r1.forward_data1;
1192 if r1.write_bram = '1' then
1193 r1.forward_data1 <= r1.req.data;
1194 r1.forward_sel1 <= r1.req.byte_sel;
1195 r1.forward_way1 <= r1.req.hit_way;
1196 r1.forward_row1 <= get_row(r1.req.real_addr);
1197 r1.forward_valid1 <= '1';
1199 if r1.dcbz = '1' then
1200 r1.forward_data1 <= (others => '0');
1202 r1.forward_data1 <= wishbone_in.dat;
1204 r1.forward_sel1 <= (others => '1');
1205 r1.forward_way1 <= replace_way;
1206 r1.forward_row1 <= r1.store_row;
1207 r1.forward_valid1 <= '0';
1210 -- On reset, clear all valid bits to force misses
1212 for i in index_t loop
1213 cache_valids(i) <= (others => '0');
1217 r1.slow_valid <= '0';
1221 -- Not useful normally but helps avoiding tons of sim warnings
1222 r1.wb.adr <= (others => '0');
1224 -- One cycle pulses reset
1225 r1.slow_valid <= '0';
1226 r1.write_bram <= '0';
1228 if r1.write_tag = '1' then
1229 -- Store new tag in selected way
1230 for i in 0 to NUM_WAYS-1 loop
1231 if i = replace_way then
1232 cache_tags(r1.store_index)((i + 1) * TAG_WIDTH - 1 downto i * TAG_WIDTH) <=
1233 (TAG_WIDTH - 1 downto TAG_BITS => '0') & r1.reload_tag;
1236 r1.store_way <= replace_way;
1237 r1.write_tag <= '0';
1240 -- Take request from r1.req if there is one there,
1241 -- else from req_op, ra, etc.
1242 if r1.full = '1' then
1246 req.valid := req_go;
1247 req.dcbz := r0.req.dcbz;
1248 req.real_addr := ra;
1249 req.data := r0.req.data;
1250 req.byte_sel := r0.req.byte_sel;
1251 req.hit_way := req_hit_way;
1252 req.same_tag := req_same_tag;
1254 -- Store the incoming request from r0, if it is a slow request
1255 -- Note that r1.full = 1 implies req_op = OP_NONE
1256 if req_op = OP_LOAD_MISS or req_op = OP_LOAD_NC or
1257 req_op = OP_STORE_MISS or req_op = OP_STORE_HIT then
1263 -- Main state machine
1266 r1.wb.adr <= req.real_addr(r1.wb.adr'left downto 0);
1269 -- Keep track of our index and way for subsequent stores.
1270 r1.store_index <= get_index(req.real_addr);
1271 r1.store_row <= get_row(req.real_addr);
1272 r1.end_row_ix <= get_row_of_line(get_row(req.real_addr)) - 1;
1273 r1.reload_tag <= get_tag(req.real_addr);
1274 r1.req.same_tag <= '1';
1276 if req.op = OP_STORE_HIT then
1277 r1.store_way <= req.hit_way;
1280 -- Reset per-row valid bits, ready for handling OP_LOAD_MISS
1281 for i in 0 to ROW_PER_LINE - 1 loop
1282 r1.rows_valid(i) <= '0';
1287 -- stay in IDLE state
1289 when OP_LOAD_MISS =>
1290 -- Normal load cache miss, start the reload machine
1292 report "cache miss real addr:" & to_hstring(req.real_addr) &
1293 " idx:" & integer'image(get_index(req.real_addr)) &
1294 " tag:" & to_hstring(get_tag(req.real_addr));
1296 -- Start the wishbone cycle
1297 r1.wb.sel <= (others => '1');
1302 -- Track that we had one request sent
1303 r1.state <= RELOAD_WAIT_ACK;
1304 r1.write_tag <= '1';
1307 r1.wb.sel <= req.byte_sel;
1311 r1.state <= NC_LOAD_WAIT_ACK;
1313 when OP_STORE_HIT | OP_STORE_MISS =>
1314 if req.dcbz = '0' then
1315 r1.wb.sel <= req.byte_sel;
1316 r1.wb.dat <= req.data;
1317 r1.state <= STORE_WAIT_ACK;
1318 r1.acks_pending <= to_unsigned(1, 3);
1320 r1.slow_valid <= '1';
1321 if req.op = OP_STORE_HIT then
1322 r1.write_bram <= '1';
1325 -- dcbz is handled much like a load miss except
1326 -- that we are writing to memory instead of reading
1328 -- Start the wishbone writes
1329 r1.wb.sel <= (others => '1');
1330 r1.wb.dat <= (others => '0');
1332 -- Handle the rest like a load miss
1333 r1.state <= RELOAD_WAIT_ACK;
1334 if req.op = OP_STORE_MISS then
1335 r1.write_tag <= '1';
1343 -- OP_NONE and OP_BAD do nothing
1344 -- OP_BAD & OP_STCX_FAIL were handled above already
1347 when OP_STCX_FAIL =>
1350 when RELOAD_WAIT_ACK =>
1351 -- Requests are all sent if stb is 0
1352 stbs_done := r1.wb.stb = '0';
1354 -- If we are still sending requests, was one accepted ?
1355 if wishbone_in.stall = '0' and not stbs_done then
1356 -- That was the last word ? We are done sending. Clear
1357 -- stb and set stbs_done so we can handle an eventual last
1358 -- ack on the same cycle.
1360 if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then
1365 -- Calculate the next row address
1366 r1.wb.adr <= next_row_addr(r1.wb.adr);
1369 -- Incoming acks processing
1370 r1.forward_valid1 <= wishbone_in.ack;
1371 if wishbone_in.ack = '1' then
1372 r1.rows_valid(r1.store_row mod ROW_PER_LINE) <= '1';
1373 -- If this is the data we were looking for, we can
1374 -- complete the request next cycle.
1375 -- Compare the whole address in case the request in
1376 -- r1.req is not the one that started this refill.
1377 if r1.full = '1' and r1.req.same_tag = '1' and
1378 ((r1.dcbz = '1' and r1.req.dcbz = '1') or
1379 (r1.dcbz = '0' and r1.req.op = OP_LOAD_MISS)) and
1380 r1.store_row = get_row(r1.req.real_addr) then
1382 r1.slow_valid <= '1';
1383 r1.forward_sel <= (others => '1');
1384 r1.use_forward1 <= '1';
1387 -- Check for completion
1388 if stbs_done and is_last_row(r1.store_row, r1.end_row_ix) then
1389 -- Complete wishbone cycle
1392 -- Cache line is now valid
1393 cache_valids(r1.store_index)(r1.store_way) <= '1';
1398 -- Increment store row counter
1399 r1.store_row <= next_row(r1.store_row);
1402 when STORE_WAIT_ACK =>
1403 stbs_done := r1.wb.stb = '0';
1404 acks := r1.acks_pending;
1405 -- Clear stb when slave accepted request
1406 if wishbone_in.stall = '0' then
1407 -- See if there is another store waiting to be done
1408 -- which is in the same real page.
1409 if req.valid = '1' then
1410 r1.wb.adr(SET_SIZE_BITS - 1 downto 0) <=
1411 req.real_addr(SET_SIZE_BITS - 1 downto 0);
1412 r1.wb.dat <= req.data;
1413 r1.wb.sel <= req.byte_sel;
1415 if acks < 7 and req.same_tag = '1' and
1416 (req.op = OP_STORE_MISS or req.op = OP_STORE_HIT) then
1419 if req.op = OP_STORE_HIT then
1420 r1.write_bram <= '1';
1423 r1.slow_valid <= '1';
1431 -- Got ack ? See if complete.
1432 if wishbone_in.ack = '1' then
1433 if stbs_done and acks = 1 then
1440 r1.acks_pending <= acks;
1442 when NC_LOAD_WAIT_ACK =>
1443 -- Clear stb when slave accepted request
1444 if wishbone_in.stall = '0' then
1448 -- Got ack ? complete.
1449 if wishbone_in.ack = '1' then
1452 r1.slow_valid <= '1';
1453 r1.forward_sel <= (others => '1');
1454 r1.use_forward1 <= '1';
1463 dc_log: if LOG_LENGTH > 0 generate
1464 signal log_data : std_ulogic_vector(19 downto 0);
1466 dcache_log: process(clk)
1468 if rising_edge(clk) then
1469 log_data <= r1.wb.adr(5 downto 3) &
1472 r1.wb.stb & r1.wb.cyc &
1475 std_ulogic_vector(to_unsigned(op_t'pos(req_op), 3)) &
1477 std_ulogic_vector(to_unsigned(tlb_hit_way, 3)) &
1479 std_ulogic_vector(to_unsigned(state_t'pos(r1.state), 3));
1482 log_out <= log_data;