2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
19 use work.wishbone_types.all;
24 LINE_SIZE : positive := 64;
25 -- Number of lines in a set
26 NUM_LINES : positive := 32;
28 NUM_WAYS : positive := 4
34 d_in : in Loadstore1ToDcacheType;
35 d_out : out DcacheToLoadstore1Type;
37 stall_out : out std_ulogic;
39 wishbone_out : out wishbone_master_out;
40 wishbone_in : in wishbone_slave_out
44 architecture rtl of dcache is
45 -- BRAM organisation: We never access more than wishbone_data_bits at
46 -- a time so to save resources we make the array only that wide, and
47 -- use consecutive indices for to make a cache "line"
49 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
50 constant ROW_SIZE : natural := wishbone_data_bits / 8;
51 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
52 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
53 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
55 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
57 -- Bit fields counts in the address
59 -- ROW_BITS is the number of bits to select a row
60 constant ROW_BITS : natural := log2(BRAM_ROWS);
61 -- ROW_LINEBITS is the number of bits to select a row within a line
62 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
63 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
64 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
65 -- ROW_OFF_BITS is the number of bits for the offset in a row
66 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
67 -- INDEX_BITS is the number if bits to select a cache line
68 constant INDEX_BITS : natural := log2(NUM_LINES);
69 -- TAG_BITS is the number of bits of the tag part of the address
70 constant TAG_BITS : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
71 -- WAY_BITS is the number of bits to select a way
72 constant WAY_BITS : natural := log2(NUM_WAYS);
74 -- Example of layout for 32 lines of 64 bytes:
76 -- .. tag |index| line |
78 -- .. | |---| | ROW_LINEBITS (3)
79 -- .. | |--- - --| LINE_OFF_BITS (6)
80 -- .. | |- --| ROW_OFF_BITS (3)
81 -- .. |----- ---| | ROW_BITS (8)
82 -- .. |-----| | INDEX_BITS (5)
83 -- .. --------| | TAG_BITS (53)
85 subtype row_t is integer range 0 to BRAM_ROWS-1;
86 subtype index_t is integer range 0 to NUM_LINES-1;
87 subtype way_t is integer range 0 to NUM_WAYS-1;
89 -- The cache data BRAM organized as described above for each way
90 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
92 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
93 -- not handle a clean (commented) definition of the cache tags as a 3d
94 -- memory. For now, work around it by putting all the tags
95 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
96 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
97 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
98 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
99 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
100 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
102 -- The cache valid bits
103 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
104 type cache_valids_t is array(index_t) of cache_way_valids_t;
106 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
107 signal cache_tags : cache_tags_array_t;
108 signal cache_valids : cache_valids_t;
110 attribute ram_style : string;
111 attribute ram_style of cache_tags : signal is "distributed";
113 signal r0 : Loadstore1ToDcacheType;
115 -- Type of operation on a "valid" input
116 type op_t is (OP_NONE,
117 OP_LOAD_HIT, -- Cache hit on load
118 OP_LOAD_MISS, -- Load missing cache
119 OP_LOAD_NC, -- Non-cachable load
120 OP_BAD, -- BAD: Cache hit on NC load/store
121 OP_STORE_HIT, -- Store hitting cache
122 OP_STORE_MISS); -- Store missing cache
124 -- Cache state machine
125 type state_t is (IDLE, -- Normal load hit processing
126 RELOAD_WAIT_ACK, -- Cache reload wait ack
127 FINISH_LD_MISS, -- Extra cycle after load miss
128 STORE_WAIT_ACK, -- Store wait ack
129 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
133 -- Dcache operations:
135 -- In order to make timing, we use the BRAMs with an output buffer,
136 -- which means that the BRAM output is delayed by an extra cycle.
138 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
141 -- All other operations are handled via stalling in the first stage.
143 -- The second stage can thus complete a hit at the same time as the
144 -- first stage emits a stall for a complex op.
147 -- First stage register, contains state for stage 1 of load hits
148 -- and for the state machine used by all other operations
150 type reg_stage_1_t is record
151 -- Latch the complete request from ls1
152 req : Loadstore1ToDcacheType;
156 hit_load_valid : std_ulogic;
158 -- Data buffer for "slow" read ops (load miss and NC loads).
159 slow_data : std_ulogic_vector(63 downto 0);
160 slow_valid : std_ulogic;
162 -- Signal to complete a failed stcx.
163 stcx_fail : std_ulogic;
165 -- Cache miss state (reload state machine)
167 wb : wishbone_master_out;
170 store_index : index_t;
173 signal r1 : reg_stage_1_t;
175 -- Reservation information
177 type reservation_t is record
179 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
182 signal reservation : reservation_t;
184 -- Async signals on incoming request
185 signal req_index : index_t;
186 signal req_row : row_t;
187 signal req_hit_way : way_t;
188 signal req_tag : cache_tag_t;
189 signal req_op : op_t;
190 signal req_data : std_ulogic_vector(63 downto 0);
191 signal req_laddr : std_ulogic_vector(63 downto 0);
193 signal early_req_row : row_t;
195 signal cancel_store : std_ulogic;
196 signal set_rsrv : std_ulogic;
197 signal clear_rsrv : std_ulogic;
199 -- Cache RAM interface
200 type cache_ram_out_t is array(way_t) of cache_row_t;
201 signal cache_out : cache_ram_out_t;
203 -- PLRU output interface
204 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
205 signal plru_victim : plru_out_t;
206 signal replace_way : way_t;
208 -- Wishbone read/write/cache write formatting signals
209 signal bus_sel : std_ulogic_vector(7 downto 0);
212 -- Helper functions to decode incoming requests
215 -- Return the cache line index (tag index) for an address
216 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
218 return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
221 -- Return the cache row index (data memory) for an address
222 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
224 return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
227 -- Returns whether this is the last row of a line
228 function is_last_row_addr(addr: wishbone_addr_type) return boolean is
229 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
231 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
234 -- Returns whether this is the last row of a line
235 function is_last_row(row: row_t) return boolean is
236 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
237 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
239 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
240 return row_v(ROW_LINEBITS-1 downto 0) = ones;
243 -- Return the address of the next row in the current cache line
244 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
245 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
246 variable result : wishbone_addr_type;
248 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
249 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
250 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
252 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
256 -- Return the next row in the current cache line. We use a dedicated
257 -- function in order to limit the size of the generated adder to be
258 -- only the bits within a cache line (3 bits with default settings)
260 function next_row(row: row_t) return row_t is
261 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
262 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
263 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
265 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
266 row_idx := row_v(ROW_LINEBITS-1 downto 0);
267 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
268 return to_integer(unsigned(row_v));
271 -- Get the tag value from the address
272 function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
274 return addr(63 downto 64-TAG_BITS);
277 -- Read a tag from a tag memory row
278 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
280 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
283 -- Write a tag to tag memory row
284 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
287 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
292 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
293 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
294 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
295 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
296 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
297 report "geometry bits don't add up" severity FAILURE;
298 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
299 report "geometry bits don't add up" severity FAILURE;
300 assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
301 report "geometry bits don't add up" severity FAILURE;
302 assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
303 report "geometry bits don't add up" severity FAILURE;
304 assert (64 = wishbone_data_bits)
305 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
308 maybe_plrus: if NUM_WAYS > 1 generate
310 plrus: for i in 0 to NUM_LINES-1 generate
312 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
313 signal plru_acc_en : std_ulogic;
314 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
317 plru : entity work.plru
325 acc_en => plru_acc_en,
329 process(req_index, req_op, req_hit_way, plru_out)
332 if (req_op = OP_LOAD_HIT or
333 req_op = OP_STORE_HIT) and req_index = i then
338 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
339 plru_victim(i) <= plru_out;
344 -- Latch the request in r0 as long as we're not stalling
345 stage_0 : process(clk)
347 if rising_edge(clk) then
350 elsif stall_out = '0' then
356 -- Cache request parsing and hit detection
357 dcache_request : process(all)
358 variable is_hit : std_ulogic;
359 variable hit_way : way_t;
361 variable tmp : std_ulogic_vector(63 downto 0);
362 variable data : std_ulogic_vector(63 downto 0);
363 variable opsel : std_ulogic_vector(3 downto 0);
364 variable go : std_ulogic;
366 -- Extract line, row and tag from request
367 req_index <= get_index(r0.addr);
368 req_row <= get_row(r0.addr);
369 req_tag <= get_tag(r0.addr);
371 -- Only do anything if not being stalled by stage 1
372 go := r0.valid and not stall_out;
374 -- Calculate address of beginning of cache line, will be
375 -- used for cache miss processing if needed
377 req_laddr <= r0.addr(63 downto LINE_OFF_BITS) &
378 (LINE_OFF_BITS-1 downto 0 => '0');
380 -- Test if pending request is a hit on any way
384 if go = '1' and cache_valids(req_index)(i) = '1' then
385 if read_tag(i, cache_tags(req_index)) = req_tag then
392 -- The way that matched on a hit
393 req_hit_way <= hit_way;
395 -- The way to replace on a miss
396 replace_way <= to_integer(unsigned(plru_victim(req_index)));
398 -- Combine the request and cache his status to decide what
399 -- operation needs to be done
401 opsel := go & r0.load & r0.nc & is_hit;
403 when "1101" => op := OP_LOAD_HIT;
404 when "1100" => op := OP_LOAD_MISS;
405 when "1110" => op := OP_LOAD_NC;
406 when "1001" => op := OP_STORE_HIT;
407 when "1000" => op := OP_STORE_MISS;
408 when "1010" => op := OP_STORE_MISS;
409 when "1011" => op := OP_BAD;
410 when "1111" => op := OP_BAD;
411 when others => op := OP_NONE;
416 -- Version of the row number that is valid one cycle earlier
417 -- in the cases where we need to read the cache data BRAM.
418 -- If we're stalling then we need to keep reading the last
420 if stall_out = '0' then
421 early_req_row <= get_row(d_in.addr);
423 early_req_row <= req_row;
427 -- Wire up wishbone request latch out of stage 1
428 wishbone_out <= r1.wb;
430 -- TODO: Generate errors
431 -- err_nc_collision <= '1' when req_op = OP_BAD else '0';
433 -- Generate stalls from stage 1 state machine
434 stall_out <= '1' when r1.state /= IDLE else '0';
436 -- Handle load-with-reservation and store-conditional instructions
437 reservation_comb: process(all)
442 if stall_out = '0' and r0.valid = '1' and r0.reserve = '1' then
443 -- XXX generate alignment interrupt if address is not aligned
444 -- XXX or if r0.nc = '1'
445 if r0.load = '1' then
446 -- load with reservation
451 if reservation.valid = '0' or
452 r0.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
459 reservation_reg: process(clk)
461 if rising_edge(clk) then
462 if rst = '1' or clear_rsrv = '1' then
463 reservation.valid <= '0';
464 elsif set_rsrv = '1' then
465 reservation.valid <= '1';
466 reservation.addr <= r0.addr(63 downto LINE_OFF_BITS);
471 -- Return data for loads & completion control logic
473 writeback_control: process(all)
476 -- The mux on d_out.data defaults to the normal load hit case.
478 d_out.data <= cache_out(r1.hit_way);
479 d_out.store_done <= '0';
481 -- We have a valid load or store hit or we just completed a slow
482 -- op such as a load miss, a NC load or a store
484 -- Note: the load hit is delayed by one cycle. However it can still
485 -- not collide with r.slow_valid (well unless I miscalculated) because
486 -- slow_valid can only be set on a subsequent request and not on its
487 -- first cycle (the state machine must have advanced), which makes
488 -- slow_valid at least 2 cycles from the previous hit_load_valid.
491 -- Sanity: Only one of these must be set in any given cycle
492 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
493 "unexpected slow_valid collision with stcx_fail"
495 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
496 "unexpected hit_load_delayed collision with slow_valid"
499 -- Load hit case is the standard path
500 if r1.hit_load_valid = '1' then
501 report "completing load hit";
505 -- Slow ops (load miss, NC, stores)
506 if r1.slow_valid = '1' then
507 -- If it's a load, enable register writeback and switch
511 -- Read data comes from the slow data latch
512 d_out.data <= r1.slow_data;
514 d_out.store_done <= '1';
516 report "completing store or load miss";
520 if r1.stcx_fail = '1' then
521 d_out.store_done <= '0';
528 -- Generate a cache RAM for each way. This handles the normal
529 -- reads, writes from reloads and the special store-hit update
532 -- Note: the BRAMs have an extra read buffer, meaning the output
533 -- is pipelined an extra cycle. This differs from the
534 -- icache. The writeback logic needs to take that into
535 -- account by using 1-cycle delayed signals for load hits.
537 rams: for i in 0 to NUM_WAYS-1 generate
538 signal do_read : std_ulogic;
539 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
540 signal do_write : std_ulogic;
541 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
542 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
543 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
544 signal dout : cache_row_t;
546 way: entity work.cache_ram
548 ROW_BITS => ROW_BITS,
549 WIDTH => wishbone_data_bits,
563 variable tmp_adr : std_ulogic_vector(63 downto 0);
564 variable reloading : boolean;
568 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
569 cache_out(i) <= dout;
573 -- Defaults to wishbone read responses (cache refill),
575 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
576 -- other than the current state. Only the do_write signal is.
578 if r1.state = IDLE then
579 -- In IDLE state, the only write path is the store-hit update case
580 wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
582 wr_sel <= r0.byte_sel;
584 -- Otherwise, we might be doing a reload
585 wr_data <= wishbone_in.dat;
586 wr_sel <= (others => '1');
587 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
590 -- The two actual write cases here
592 reloading := r1.state = RELOAD_WAIT_ACK;
593 if reloading and wishbone_in.ack = '1' and r1.store_way = i then
596 if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' then
597 assert not reloading report "Store hit while in state:" &
598 state_t'image(r1.state)
606 -- Cache hit synchronous machine for the easy case. This handles load hits.
608 dcache_fast_hit : process(clk)
610 if rising_edge(clk) then
611 -- If we have a request incoming, we have to latch it as r0.valid
612 -- is only set for a single cycle. It's up to the control logic to
613 -- ensure we don't override an uncompleted request (for now we are
614 -- single issue on load/stores so we are fine, later, we can generate
615 -- a stall output if necessary).
617 if req_op /= OP_NONE and stall_out = '0' then
619 report "op:" & op_t'image(req_op) &
620 " addr:" & to_hstring(r0.addr) &
621 " nc:" & std_ulogic'image(r0.nc) &
622 " idx:" & integer'image(req_index) &
623 " tag:" & to_hstring(req_tag) &
624 " way: " & integer'image(req_hit_way);
627 -- Fast path for load/store hits. Set signals for the writeback controls.
628 if req_op = OP_LOAD_HIT then
629 r1.hit_way <= req_hit_way;
630 r1.hit_load_valid <= '1';
632 r1.hit_load_valid <= '0';
638 -- Every other case is handled by this state machine:
640 -- * Cache load miss/reload (in conjunction with "rams")
641 -- * Load hits for non-cachable forms
642 -- * Stores (the collision case is handled in "rams")
644 -- All wishbone requests generation is done here. This machine
645 -- operates at stage 1.
647 dcache_slow : process(clk)
648 variable tagset : cache_tags_set_t;
649 variable stbs_done : boolean;
651 if rising_edge(clk) then
652 -- On reset, clear all valid bits to force misses
654 for i in index_t loop
655 cache_valids(i) <= (others => '0');
658 r1.slow_valid <= '0';
662 -- Not useful normally but helps avoiding tons of sim warnings
663 r1.wb.adr <= (others => '0');
665 -- One cycle pulses reset
666 r1.slow_valid <= '0';
669 -- Main state machine
674 -- stay in IDLE state
677 -- Normal load cache miss, start the reload machine
679 report "cache miss addr:" & to_hstring(r0.addr) &
680 " idx:" & integer'image(req_index) &
681 " way:" & integer'image(replace_way) &
682 " tag:" & to_hstring(req_tag);
684 -- Force misses on that way while reloading that line
685 cache_valids(req_index)(replace_way) <= '0';
687 -- Store new tag in selected way
688 for i in 0 to NUM_WAYS-1 loop
689 if i = replace_way then
690 tagset := cache_tags(req_index);
691 write_tag(i, tagset, req_tag);
692 cache_tags(req_index) <= tagset;
696 -- Keep track of our index and way for subsequent stores.
697 r1.store_index <= req_index;
698 r1.store_way <= replace_way;
699 r1.store_row <= get_row(req_laddr);
701 -- Prep for first wishbone read. We calculate the address of
702 -- the start of the cache line and start the WB cycle
704 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
705 r1.wb.sel <= (others => '1');
710 -- Track that we had one request sent
711 r1.state <= RELOAD_WAIT_ACK;
714 r1.wb.sel <= r0.byte_sel;
715 r1.wb.adr <= r0.addr(r1.wb.adr'left downto 3) & "000";
719 r1.state <= NC_LOAD_WAIT_ACK;
721 when OP_STORE_HIT | OP_STORE_MISS =>
722 r1.wb.sel <= r0.byte_sel;
723 r1.wb.adr <= r0.addr(r1.wb.adr'left downto 3) & "000";
724 r1.wb.dat <= r0.data;
725 if cancel_store = '0' then
729 r1.state <= STORE_WAIT_ACK;
735 -- OP_NONE and OP_BAD do nothing
740 when RELOAD_WAIT_ACK =>
741 -- Requests are all sent if stb is 0
742 stbs_done := r1.wb.stb = '0';
744 -- If we are still sending requests, was one accepted ?
745 if wishbone_in.stall = '0' and not stbs_done then
746 -- That was the last word ? We are done sending. Clear
747 -- stb and set stbs_done so we can handle an eventual last
748 -- ack on the same cycle.
750 if is_last_row_addr(r1.wb.adr) then
755 -- Calculate the next row address
756 r1.wb.adr <= next_row_addr(r1.wb.adr);
759 -- Incoming acks processing
760 if wishbone_in.ack = '1' then
761 -- Is this the data we were looking for ? Latch it so
762 -- we can respond later. We don't currently complete the
763 -- pending miss request immediately, we wait for the
764 -- whole line to be loaded. The reason is that if we
765 -- did, we would potentially get new requests in while
766 -- not idle, which we don't currently know how to deal
769 if r1.store_row = get_row(r1.req.addr) then
770 r1.slow_data <= wishbone_in.dat;
773 -- Check for completion
774 if stbs_done and is_last_row(r1.store_row) then
775 -- Complete wishbone cycle
778 -- Cache line is now valid
779 cache_valids(r1.store_index)(r1.store_way) <= '1';
781 -- Don't complete and go idle until next cycle, in
782 -- case the next request is for the last dword of
783 -- the cache line we just loaded.
784 r1.state <= FINISH_LD_MISS;
787 -- Increment store row counter
788 r1.store_row <= next_row(r1.store_row);
791 when FINISH_LD_MISS =>
792 -- Write back the load data that we got
793 r1.slow_valid <= '1';
795 report "completing miss !";
797 when STORE_WAIT_ACK | NC_LOAD_WAIT_ACK =>
798 -- Clear stb when slave accepted request
799 if wishbone_in.stall = '0' then
803 -- Got ack ? complete.
804 if wishbone_in.ack = '1' then
805 if r1.state = NC_LOAD_WAIT_ACK then
806 r1.slow_data <= wishbone_in.dat;
809 r1.slow_valid <= '1';