2 -- Set associative dcache write-through
4 -- TODO (in no specific order):
6 -- * See list in icache.vhdl
7 -- * Complete load misses on the cycle when WB data comes instead of
8 -- at the end of line (this requires dealing with requests coming in
10 -- * Load with update could use one less non-pipelined cycle by moving
11 -- the register update to the pipeline bubble that exists when going
12 -- back to the IDLE state.
15 use ieee.std_logic_1164.all;
16 use ieee.numeric_std.all;
22 use work.wishbone_types.all;
27 LINE_SIZE : positive := 64;
28 -- Number of lines in a set
29 NUM_LINES : positive := 32;
31 NUM_WAYS : positive := 4
37 d_in : in Loadstore1ToDcacheType;
38 d_out : out DcacheToWritebackType;
40 stall_out : out std_ulogic;
42 wishbone_out : out wishbone_master_out;
43 wishbone_in : in wishbone_slave_out
47 architecture rtl of dcache is
48 -- BRAM organisation: We never access more than wishbone_data_bits at
49 -- a time so to save resources we make the array only that wide, and
50 -- use consecutive indices for to make a cache "line"
52 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
53 constant ROW_SIZE : natural := wishbone_data_bits / 8;
54 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
55 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
56 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
58 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
60 -- Bit fields counts in the address
62 -- ROW_BITS is the number of bits to select a row
63 constant ROW_BITS : natural := log2(BRAM_ROWS);
64 -- ROW_LINEBITS is the number of bits to select a row within a line
65 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
66 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
67 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
68 -- ROW_OFF_BITS is the number of bits for the offset in a row
69 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
70 -- INDEX_BITS is the number if bits to select a cache line
71 constant INDEX_BITS : natural := log2(NUM_LINES);
72 -- TAG_BITS is the number of bits of the tag part of the address
73 constant TAG_BITS : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
74 -- WAY_BITS is the number of bits to select a way
75 constant WAY_BITS : natural := log2(NUM_WAYS);
77 -- Example of layout for 32 lines of 64 bytes:
79 -- .. tag |index| line |
81 -- .. | |---| | ROW_LINEBITS (3)
82 -- .. | |--- - --| LINE_OFF_BITS (6)
83 -- .. | |- --| ROW_OFF_BITS (3)
84 -- .. |----- ---| | ROW_BITS (8)
85 -- .. |-----| | INDEX_BITS (5)
86 -- .. --------| | TAG_BITS (53)
88 subtype row_t is integer range 0 to BRAM_ROWS-1;
89 subtype index_t is integer range 0 to NUM_LINES-1;
90 subtype way_t is integer range 0 to NUM_WAYS-1;
92 -- The cache data BRAM organized as described above for each way
93 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
95 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
96 -- not handle a clean (commented) definition of the cache tags as a 3d
97 -- memory. For now, work around it by putting all the tags
98 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
99 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
100 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
101 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
102 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
103 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
105 -- The cache valid bits
106 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
107 type cache_valids_t is array(index_t) of cache_way_valids_t;
109 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
110 signal cache_tags : cache_tags_array_t;
111 signal cache_valids : cache_valids_t;
113 attribute ram_style : string;
114 attribute ram_style of cache_tags : signal is "distributed";
116 -- Type of operation on a "valid" input
117 type op_t is (OP_NONE,
118 OP_LOAD_HIT, -- Cache hit on load
119 OP_LOAD_MISS, -- Load missing cache
120 OP_LOAD_NC, -- Non-cachable load
121 OP_BAD, -- BAD: Cache hit on NC load/store
122 OP_STORE_HIT, -- Store hitting cache
123 OP_STORE_MISS); -- Store missing cache
125 -- Cache state machine
126 type state_t is (IDLE, -- Normal load hit processing
127 PRE_NEXT_DWORD, -- Extra state before NEXT_DWORD
128 NEXT_DWORD, -- Starting the 2nd xfer of misaligned
129 LOAD_UPDATE, -- Load with update extra cycle
130 RELOAD_WAIT_ACK, -- Cache reload wait ack
131 STORE_WAIT_ACK, -- Store wait ack
132 NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
136 -- Dcache operations:
138 -- In order to make timing, we use the BRAMs with an output buffer,
139 -- which means that the BRAM output is delayed by an extra cycle.
141 -- Thus, the dcache has a 2-stage internal pipeline for cache hits
144 -- All other operations are handled via stalling in the first stage.
146 -- The second stage can thus complete a hit at the same time as the
147 -- first stage emits a stall for a complex op.
150 -- First stage register, contains state for stage 1 of load hits
151 -- and for the state machine used by all other operations
153 type reg_stage_1_t is record
154 -- Latch the complete request from ls1
155 req : Loadstore1ToDcacheType;
159 hit_load_valid : std_ulogic;
161 -- Info for doing the second transfer of a misaligned load/store
162 two_dwords : std_ulogic;
163 second_dword : std_ulogic;
164 next_addr : std_ulogic_vector(63 downto 0);
165 next_sel : std_ulogic_vector(7 downto 0);
167 -- Register update (load/store with update)
168 update_valid : std_ulogic;
170 -- Data buffer for "slow" read ops (load miss and NC loads).
171 slow_data : std_ulogic_vector(63 downto 0);
172 slow_valid : std_ulogic;
174 -- Signal to complete a failed stcx.
175 stcx_fail : std_ulogic;
177 -- Cache miss state (reload state machine)
179 wb : wishbone_master_out;
182 store_index : index_t;
185 signal r1 : reg_stage_1_t;
187 -- Reservation information
189 type reservation_t is record
191 addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
194 signal reservation : reservation_t;
196 -- Async signals on incoming request
197 signal req_index : index_t;
198 signal req_row : row_t;
199 signal req_hit_way : way_t;
200 signal req_tag : cache_tag_t;
201 signal req_op : op_t;
202 signal req_data : std_ulogic_vector(63 downto 0);
203 signal req_addr : std_ulogic_vector(63 downto 0);
204 signal req_laddr : std_ulogic_vector(63 downto 0);
205 signal req_sel : std_ulogic_vector(7 downto 0);
206 signal next_addr : std_ulogic_vector(63 downto 0);
208 signal early_req_addr : std_ulogic_vector(11 downto 0);
209 signal early_req_row : row_t;
211 signal cancel_store : std_ulogic;
212 signal set_rsrv : std_ulogic;
213 signal clear_rsrv : std_ulogic;
215 -- Cache RAM interface
216 type cache_ram_out_t is array(way_t) of cache_row_t;
217 signal cache_out : cache_ram_out_t;
219 -- PLRU output interface
220 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
221 signal plru_victim : plru_out_t;
222 signal replace_way : way_t;
224 -- Wishbone read/write/cache write formatting signals
225 signal bus_sel : std_ulogic_vector(15 downto 0);
227 signal two_dwords : std_ulogic;
230 -- Helper functions to decode incoming requests
233 -- Return the cache line index (tag index) for an address
234 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
236 return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
239 -- Return the cache row index (data memory) for an address
240 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
242 return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
245 -- Returns whether this is the last row of a line
246 function is_last_row_addr(addr: wishbone_addr_type) return boolean is
247 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
249 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
252 -- Returns whether this is the last row of a line
253 function is_last_row(row: row_t) return boolean is
254 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
255 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
257 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
258 return row_v(ROW_LINEBITS-1 downto 0) = ones;
261 -- Return the address of the next row in the current cache line
262 function next_row_addr(addr: wishbone_addr_type) return std_ulogic_vector is
263 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
264 variable result : wishbone_addr_type;
266 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
267 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
268 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
270 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
274 -- Return the next row in the current cache line. We use a dedicated
275 -- function in order to limit the size of the generated adder to be
276 -- only the bits within a cache line (3 bits with default settings)
278 function next_row(row: row_t) return row_t is
279 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
280 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
281 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
283 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
284 row_idx := row_v(ROW_LINEBITS-1 downto 0);
285 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
286 return to_integer(unsigned(row_v));
289 -- Get the tag value from the address
290 function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
292 return addr(63 downto 64-TAG_BITS);
295 -- Read a tag from a tag memory row
296 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
298 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
301 -- Write a tag to tag memory row
302 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
305 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
308 -- Generate byte enables from sizes
309 function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
323 end function length_to_sel;
325 -- Calculate byte enables for wishbone
326 -- This returns 16 bits, giving the select signals for two transfers,
327 -- to account for unaligned loads or stores
328 function wishbone_data_sel(size : in std_logic_vector(3 downto 0);
329 address : in std_logic_vector(63 downto 0))
330 return std_ulogic_vector is
331 variable longsel : std_ulogic_vector(15 downto 0);
333 longsel := (others => '0');
334 longsel(7 downto 0) := length_to_sel(size);
335 return std_ulogic_vector(shift_left(unsigned(longsel),
336 to_integer(unsigned(address(2 downto 0)))));
337 end function wishbone_data_sel;
341 assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
342 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
343 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
344 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
345 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
346 report "geometry bits don't add up" severity FAILURE;
347 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
348 report "geometry bits don't add up" severity FAILURE;
349 assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
350 report "geometry bits don't add up" severity FAILURE;
351 assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
352 report "geometry bits don't add up" severity FAILURE;
353 assert (64 = wishbone_data_bits)
354 report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
357 maybe_plrus: if NUM_WAYS > 1 generate
359 plrus: for i in 0 to NUM_LINES-1 generate
361 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
362 signal plru_acc_en : std_ulogic;
363 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
366 plru : entity work.plru
374 acc_en => plru_acc_en,
378 process(req_index, req_op, req_hit_way, plru_out)
381 if (req_op = OP_LOAD_HIT or
382 req_op = OP_STORE_HIT) and req_index = i then
387 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
388 plru_victim(i) <= plru_out;
393 -- Wishbone read and write and BRAM write sel bits generation
394 bus_sel <= wishbone_data_sel(d_in.length, d_in.addr);
396 -- See if the operation crosses two doublewords
397 two_dwords <= or (bus_sel(15 downto 8));
399 -- Cache request parsing and hit detection
400 dcache_request : process(all)
401 variable is_hit : std_ulogic;
402 variable hit_way : way_t;
404 variable tmp : std_ulogic_vector(63 downto 0);
405 variable data : std_ulogic_vector(63 downto 0);
406 variable opsel : std_ulogic_vector(3 downto 0);
407 variable go : std_ulogic;
408 variable is_load : std_ulogic;
409 variable is_nc : std_ulogic;
411 -- Extract line, row and tag from request
412 if r1.state /= NEXT_DWORD then
413 req_addr <= d_in.addr;
414 req_data <= d_in.data;
415 req_sel <= bus_sel(7 downto 0);
417 is_load := d_in.load;
421 req_addr <= r1.next_addr;
422 req_data <= r1.req.data;
423 req_sel <= r1.next_sel;
425 is_load := r1.req.load;
429 req_index <= get_index(req_addr);
430 req_row <= get_row(req_addr);
431 req_tag <= get_tag(req_addr);
433 -- Calculate address of beginning of cache line, will be
434 -- used for cache miss processing if needed
436 req_laddr <= req_addr(63 downto LINE_OFF_BITS) &
437 (LINE_OFF_BITS-1 downto 0 => '0');
439 -- Address of next doubleword, used for unaligned accesses
440 next_addr <= std_ulogic_vector(unsigned(d_in.addr(63 downto 3)) + 1) & "000";
442 -- Test if pending request is a hit on any way
446 if go = '1' and cache_valids(req_index)(i) = '1' then
447 if read_tag(i, cache_tags(req_index)) = req_tag then
454 -- The way that matched on a hit
455 req_hit_way <= hit_way;
457 -- The way to replace on a miss
458 replace_way <= to_integer(unsigned(plru_victim(req_index)));
460 -- Combine the request and cache his status to decide what
461 -- operation needs to be done
463 opsel := go & is_load & is_nc & is_hit;
465 when "1101" => op := OP_LOAD_HIT;
466 when "1100" => op := OP_LOAD_MISS;
467 when "1110" => op := OP_LOAD_NC;
468 when "1001" => op := OP_STORE_HIT;
469 when "1000" => op := OP_STORE_MISS;
470 when "1010" => op := OP_STORE_MISS;
471 when "1011" => op := OP_BAD;
472 when "1111" => op := OP_BAD;
473 when others => op := OP_NONE;
478 -- Versions of the address and row number that are valid one cycle earlier
479 -- in the cases where we need to read the cache data BRAM.
480 if r1.state = IDLE and op = OP_LOAD_HIT and two_dwords = '1' then
481 early_req_addr <= next_addr(11 downto 0);
482 elsif r1.state /= IDLE and r1.two_dwords = '1' and r1.second_dword = '0' then
483 early_req_addr <= r1.next_addr(11 downto 0);
485 early_req_addr <= d_in.early_low_addr;
487 early_req_row <= get_row(x"0000000000000" & early_req_addr);
490 -- Wire up wishbone request latch out of stage 1
491 wishbone_out <= r1.wb;
493 -- TODO: Generate errors
494 -- err_nc_collision <= '1' when req_op = OP_BAD else '0';
496 -- Generate stalls from stage 1 state machine
497 stall_out <= '1' when r1.state /= IDLE else '0';
499 -- Handle load-with-reservation and store-conditional instructions
500 reservation_comb: process(all)
505 if d_in.valid = '1' and d_in.reserve = '1' then
506 -- XXX generate alignment interrupt if address is not aligned
507 -- XXX or if d_in.nc = '1'
508 if d_in.load = '1' then
509 -- load with reservation
514 if reservation.valid = '0' or
515 d_in.addr(63 downto LINE_OFF_BITS) /= reservation.addr then
522 reservation_reg: process(clk)
524 if rising_edge(clk) then
525 if rst = '1' or clear_rsrv = '1' then
526 reservation.valid <= '0';
527 elsif set_rsrv = '1' then
528 reservation.valid <= '1';
529 reservation.addr <= d_in.addr(63 downto LINE_OFF_BITS);
534 -- Writeback (loads and reg updates) & completion control logic
536 writeback_control: process(all)
539 -- The mux on d_out.write reg defaults to the normal load hit case.
540 d_out.write_enable <= '0';
542 d_out.write_reg <= r1.req.write_reg;
543 d_out.write_data <= cache_out(r1.hit_way);
544 d_out.write_len <= r1.req.length;
545 d_out.write_shift <= r1.req.addr(2 downto 0);
546 d_out.sign_extend <= r1.req.sign_extend;
547 d_out.byte_reverse <= r1.req.byte_reverse;
548 d_out.second_word <= r1.second_dword;
549 d_out.xerc <= r1.req.xerc;
550 d_out.rc <= '0'; -- loads never have rc=1
551 d_out.store_done <= '0';
553 -- We have a valid load or store hit or we just completed a slow
554 -- op such as a load miss, a NC load or a store
556 -- Note: the load hit is delayed by one cycle. However it can still
557 -- not collide with r.slow_valid (well unless I miscalculated) because
558 -- slow_valid can only be set on a subsequent request and not on its
559 -- first cycle (the state machine must have advanced), which makes
560 -- slow_valid at least 2 cycles from the previous hit_load_valid.
563 -- Sanity: Only one of these must be set in any given cycle
564 assert (r1.update_valid and r1.hit_load_valid) /= '1' report
565 "unexpected hit_load_delayed collision with update_valid"
567 assert (r1.slow_valid and r1.stcx_fail) /= '1' report
568 "unexpected slow_valid collision with stcx_fail"
570 assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid) /= '1' report
571 "unexpected hit_load_delayed collision with slow_valid"
573 assert ((r1.slow_valid or r1.stcx_fail) and r1.update_valid) /= '1' report
574 "unexpected update_valid collision with slow_valid or stcx_fail"
577 -- Load hit case is the standard path
578 if r1.hit_load_valid = '1' then
579 d_out.write_enable <= '1';
581 -- If there isn't another dword to go and
582 -- it's not a load with update, complete it now
583 if (r1.second_dword or not r1.two_dwords) = '1' and
584 r1.req.update = '0' then
585 report "completing load hit";
590 -- Slow ops (load miss, NC, stores)
591 if r1.slow_valid = '1' then
592 -- If it's a load, enable register writeback and switch
596 d_out.write_reg <= r1.req.write_reg;
597 d_out.write_enable <= '1';
599 -- Read data comes from the slow data latch, formatter
600 -- from the latched request.
602 d_out.write_data <= r1.slow_data;
603 d_out.write_shift <= r1.req.addr(2 downto 0);
604 d_out.sign_extend <= r1.req.sign_extend;
605 d_out.byte_reverse <= r1.req.byte_reverse;
606 d_out.write_len <= r1.req.length;
607 d_out.xerc <= r1.req.xerc;
608 d_out.second_word <= r1.second_dword;
610 d_out.rc <= r1.req.rc;
611 d_out.store_done <= '1';
613 -- If it's a store or a non-update load form, complete now
614 -- unless we need to do another dword transfer
615 if (r1.req.load = '0' or r1.req.update = '0') and
616 (r1.two_dwords = '0' or r1.second_dword = '1') then
617 report "completing store or load miss";
622 if r1.stcx_fail = '1' then
623 d_out.rc <= r1.req.rc;
624 d_out.store_done <= '0';
628 -- We have a register update to do.
629 if r1.update_valid = '1' then
630 d_out.write_enable <= '1';
631 d_out.write_reg <= r1.req.update_reg;
633 -- Change the read data mux to the address that's going into
634 -- the register and the formatter does nothing.
636 d_out.write_data <= r1.req.addr;
637 d_out.write_shift <= "000";
638 d_out.write_len <= "1000";
639 d_out.sign_extend <= '0';
640 d_out.byte_reverse <= '0';
641 d_out.xerc <= r1.req.xerc;
642 d_out.second_word <= '0';
644 -- If it was a load, this completes the operation (load with
647 if r1.req.load = '1' then
648 report "completing after load update";
656 -- Generate a cache RAM for each way. This handles the normal
657 -- reads, writes from reloads and the special store-hit update
660 -- Note: the BRAMs have an extra read buffer, meaning the output
661 -- is pipelined an extra cycle. This differs from the
662 -- icache. The writeback logic needs to take that into
663 -- account by using 1-cycle delayed signals for load hits.
665 rams: for i in 0 to NUM_WAYS-1 generate
666 signal do_read : std_ulogic;
667 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
668 signal do_write : std_ulogic;
669 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
670 signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
671 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
672 signal dout : cache_row_t;
674 way: entity work.cache_ram
676 ROW_BITS => ROW_BITS,
677 WIDTH => wishbone_data_bits,
691 variable tmp_adr : std_ulogic_vector(63 downto 0);
692 variable reloading : boolean;
696 rd_addr <= std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
697 cache_out(i) <= dout;
701 -- Defaults to wishbone read responses (cache refill),
703 -- For timing, the mux on wr_data/sel/addr is not dependent on anything
704 -- other than the current state. Only the do_write signal is.
706 if r1.state = IDLE or r1.state = NEXT_DWORD then
707 -- In these states, the only write path is the store-hit update case
708 wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
712 -- Otherwise, we might be doing a reload
713 wr_data <= wishbone_in.dat;
714 wr_sel <= (others => '1');
715 wr_addr <= std_ulogic_vector(to_unsigned(r1.store_row, ROW_BITS));
718 -- The two actual write cases here
720 reloading := r1.state = RELOAD_WAIT_ACK;
721 if reloading and wishbone_in.ack = '1' and r1.store_way = i then
724 if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' then
725 assert not reloading report "Store hit while in state:" &
726 state_t'image(r1.state)
734 -- Cache hit synchronous machine for the easy case. This handles
735 -- non-update form load hits
737 dcache_fast_hit : process(clk)
739 if rising_edge(clk) then
740 -- If we have a request incoming, we have to latch it as d_in.valid
741 -- is only set for a single cycle. It's up to the control logic to
742 -- ensure we don't override an uncompleted request (for now we are
743 -- single issue on load/stores so we are fine, later, we can generate
744 -- a stall output if necessary).
746 if req_op /= OP_NONE and d_in.valid = '1' then
748 r1.second_dword <= '0';
749 r1.two_dwords <= two_dwords;
750 r1.next_addr <= next_addr;
751 r1.next_sel <= bus_sel(15 downto 8);
753 report "op:" & op_t'image(req_op) &
754 " addr:" & to_hstring(d_in.addr) &
755 " upd:" & std_ulogic'image(d_in.update) &
756 " nc:" & std_ulogic'image(d_in.nc) &
757 " reg:" & to_hstring(d_in.write_reg) &
758 " idx:" & integer'image(req_index) &
759 " tag:" & to_hstring(req_tag) &
760 " way: " & integer'image(req_hit_way);
761 elsif r1.state = NEXT_DWORD then
762 r1.second_dword <= '1';
765 -- Fast path for load/store hits. Set signals for the writeback controls.
766 if req_op = OP_LOAD_HIT then
767 r1.hit_way <= req_hit_way;
768 r1.hit_load_valid <= '1';
770 r1.hit_load_valid <= '0';
776 -- Every other case is handled by this state machine:
778 -- * Cache load miss/reload (in conjunction with "rams")
779 -- * Load hits for update forms
780 -- * Load hits for non-cachable forms
781 -- * Stores (the collision case is handled in "rams")
783 -- All wishbone requests generation is done here. This machine
784 -- operates at stage 1.
786 dcache_slow : process(clk)
787 variable tagset : cache_tags_set_t;
788 variable stbs_done : boolean;
790 if rising_edge(clk) then
791 -- On reset, clear all valid bits to force misses
793 for i in index_t loop
794 cache_valids(i) <= (others => '0');
797 r1.slow_valid <= '0';
798 r1.update_valid <= '0';
802 -- Not useful normally but helps avoiding tons of sim warnings
803 r1.wb.adr <= (others => '0');
805 -- One cycle pulses reset
806 r1.slow_valid <= '0';
807 r1.update_valid <= '0';
810 -- We cannot currently process a new request when not idle
811 assert d_in.valid = '0' or r1.state = IDLE report "request " &
812 op_t'image(req_op) & " while in state " & state_t'image(r1.state)
815 -- Main state machine
817 when IDLE | NEXT_DWORD =>
820 if r1.state = IDLE then
821 -- If the load is misaligned then we will need to start
823 if two_dwords = '1' then
824 r1.state <= NEXT_DWORD;
825 elsif d_in.update = '1' then
826 r1.state <= LOAD_UPDATE;
829 if r1.req.update = '1' then
830 r1.state <= LOAD_UPDATE;
837 -- Normal load cache miss, start the reload machine
839 report "cache miss addr:" & to_hstring(req_addr) &
840 " idx:" & integer'image(req_index) &
841 " way:" & integer'image(replace_way) &
842 " tag:" & to_hstring(req_tag);
844 -- Force misses on that way while reloading that line
845 cache_valids(req_index)(replace_way) <= '0';
847 -- Store new tag in selected way
848 for i in 0 to NUM_WAYS-1 loop
849 if i = replace_way then
850 tagset := cache_tags(req_index);
851 write_tag(i, tagset, req_tag);
852 cache_tags(req_index) <= tagset;
856 -- Keep track of our index and way for subsequent stores.
857 r1.store_index <= req_index;
858 r1.store_way <= replace_way;
859 r1.store_row <= get_row(req_laddr);
861 -- Prep for first wishbone read. We calculate the address of
862 -- the start of the cache line and start the WB cycle
864 r1.wb.adr <= req_laddr(r1.wb.adr'left downto 0);
865 r1.wb.sel <= (others => '1');
870 -- Track that we had one request sent
871 r1.state <= RELOAD_WAIT_ACK;
874 r1.wb.sel <= req_sel;
875 r1.wb.adr <= req_addr(r1.wb.adr'left downto 3) & "000";
879 r1.state <= NC_LOAD_WAIT_ACK;
881 when OP_STORE_HIT | OP_STORE_MISS =>
882 -- For store-with-update do the register update
883 r1.update_valid <= d_in.valid and d_in.update;
884 r1.wb.sel <= req_sel;
885 r1.wb.adr <= req_addr(r1.wb.adr'left downto 3) & "000";
886 r1.wb.dat <= req_data;
887 if cancel_store = '0' then
891 r1.state <= STORE_WAIT_ACK;
897 -- OP_NONE and OP_BAD do nothing
902 when PRE_NEXT_DWORD =>
903 r1.state <= NEXT_DWORD;
905 when RELOAD_WAIT_ACK =>
906 -- Requests are all sent if stb is 0
907 stbs_done := r1.wb.stb = '0';
909 -- If we are still sending requests, was one accepted ?
910 if wishbone_in.stall = '0' and not stbs_done then
911 -- That was the last word ? We are done sending. Clear
912 -- stb and set stbs_done so we can handle an eventual last
913 -- ack on the same cycle.
915 if is_last_row_addr(r1.wb.adr) then
920 -- Calculate the next row address
921 r1.wb.adr <= next_row_addr(r1.wb.adr);
924 -- Incoming acks processing
925 if wishbone_in.ack = '1' then
926 -- Is this the data we were looking for ? Latch it so
927 -- we can respond later. We don't currently complete the
928 -- pending miss request immediately, we wait for the
929 -- whole line to be loaded. The reason is that if we
930 -- did, we would potentially get new requests in while
931 -- not idle, which we don't currently know how to deal
934 if r1.store_row = get_row(r1.req.addr) then
935 r1.slow_data <= wishbone_in.dat;
938 -- Check for completion
939 if stbs_done and is_last_row(r1.store_row) then
940 -- Complete wishbone cycle
943 -- Cache line is now valid
944 cache_valids(r1.store_index)(r1.store_way) <= '1';
946 -- Write back the load data that we got, and start
947 -- the second dword if necessary. Otherwise, see if
948 -- we also need to do the deferred update cycle.
949 r1.slow_valid <= '1';
950 if r1.two_dwords and not r1.second_dword then
951 r1.state <= PRE_NEXT_DWORD;
952 elsif r1.req.update = '1' then
953 r1.state <= LOAD_UPDATE;
954 report "completing miss with load-update !";
957 report "completing miss !";
961 -- Increment store row counter
962 r1.store_row <= next_row(r1.store_row);
966 -- We need the extra cycle to complete a load with update
967 r1.update_valid <= '1';
970 when STORE_WAIT_ACK | NC_LOAD_WAIT_ACK =>
971 -- Clear stb when slave accepted request
972 if wishbone_in.stall = '0' then
976 -- Got ack ? complete.
977 if wishbone_in.ack = '1' then
978 if r1.two_dwords and not r1.second_dword then
979 r1.state <= NEXT_DWORD;
980 elsif r1.state = NC_LOAD_WAIT_ACK and r1.req.update = '1' then
981 r1.state <= LOAD_UPDATE;
985 if r1.state = NC_LOAD_WAIT_ACK then
986 r1.slow_data <= wishbone_in.dat;
988 r1.slow_valid <= '1';