2 use ieee.std_logic_1164.all;
6 use work.wishbone_types.all;
11 architecture behave of dcache_tb is
12 signal clk : std_ulogic;
13 signal rst : std_ulogic;
15 signal d_in : Loadstore1ToDcacheType;
16 signal d_out : DcacheToLoadstore1Type;
18 signal m_in : MmuToDcacheType;
19 signal m_out : DcacheToMmuType;
21 signal wb_bram_in : wishbone_master_out;
22 signal wb_bram_out : wishbone_slave_out;
24 constant clk_period : time := 10 ns;
26 dcache0: entity work.dcache
38 wishbone_out => wb_bram_in,
39 wishbone_in => wb_bram_out
43 bram0: entity work.wishbone_bram_wrapper
46 RAM_INIT_FILE => "icache_test.bin"
51 wishbone_in => wb_bram_in,
52 wishbone_out => wb_bram_out
58 wait for clk_period/2;
60 wait for clk_period/2;
66 wait for 2*clk_period;
77 d_in.addr <= (others => '0');
78 d_in.data <= (others => '0');
80 m_in.addr <= (others => '0');
81 m_in.pte <= (others => '0');
83 wait for 4*clk_period;
84 wait until rising_edge(clk);
86 -- Cacheable read of address 4
89 d_in.addr <= x"0000000000000004";
91 wait until rising_edge(clk);
94 wait until rising_edge(clk) and d_out.valid = '1';
95 assert d_out.data = x"0000000100000000"
96 report "data @" & to_hstring(d_in.addr) &
97 "=" & to_hstring(d_out.data) &
98 " expected 0000000100000000"
100 -- wait for clk_period;
102 -- Cacheable read of address 30
105 d_in.addr <= x"0000000000000030";
107 wait until rising_edge(clk);
110 wait until rising_edge(clk) and d_out.valid = '1';
111 assert d_out.data = x"0000000D0000000C"
112 report "data @" & to_hstring(d_in.addr) &
113 "=" & to_hstring(d_out.data) &
114 " expected 0000000D0000000C"
117 -- Non-cacheable read of address 100
120 d_in.addr <= x"0000000000000100";
122 wait until rising_edge(clk);
124 wait until rising_edge(clk) and d_out.valid = '1';
125 assert d_out.data = x"0000004100000040"
126 report "data @" & to_hstring(d_in.addr) &
127 "=" & to_hstring(d_out.data) &
128 " expected 0000004100000040"
131 wait until rising_edge(clk);
132 wait until rising_edge(clk);
133 wait until rising_edge(clk);
134 wait until rising_edge(clk);