2 use ieee.std_logic_1164.all;
6 use work.wishbone_types.all;
11 architecture behave of dcache_tb is
12 signal clk : std_ulogic;
13 signal rst : std_ulogic;
15 signal d_in : Loadstore1ToDcacheType;
16 signal d_out : DcacheToLoadstore1Type;
18 signal wb_bram_in : wishbone_master_out;
19 signal wb_bram_out : wishbone_slave_out;
21 constant clk_period : time := 10 ns;
23 dcache0: entity work.dcache
33 wishbone_out => wb_bram_in,
34 wishbone_in => wb_bram_out
38 bram0: entity work.wishbone_bram_wrapper
41 RAM_INIT_FILE => "icache_test.bin"
46 wishbone_in => wb_bram_in,
47 wishbone_out => wb_bram_out
53 wait for clk_period/2;
55 wait for clk_period/2;
61 wait for 2*clk_period;
72 d_in.addr <= (others => '0');
73 d_in.data <= (others => '0');
75 wait for 4*clk_period;
76 wait until rising_edge(clk);
78 -- Cacheable read of address 4
81 d_in.addr <= x"0000000000000004";
83 wait until rising_edge(clk);
86 wait until rising_edge(clk) and d_out.valid = '1';
87 assert d_out.data = x"0000000100000000"
88 report "data @" & to_hstring(d_in.addr) &
89 "=" & to_hstring(d_out.data) &
90 " expected 0000000100000000"
92 -- wait for clk_period;
94 -- Cacheable read of address 30
97 d_in.addr <= x"0000000000000030";
99 wait until rising_edge(clk);
102 wait until rising_edge(clk) and d_out.valid = '1';
103 assert d_out.data = x"0000000D0000000C"
104 report "data @" & to_hstring(d_in.addr) &
105 "=" & to_hstring(d_out.data) &
106 " expected 0000000D0000000C"
109 -- Non-cacheable read of address 100
112 d_in.addr <= x"0000000000000100";
114 wait until rising_edge(clk);
116 wait until rising_edge(clk) and d_out.valid = '1';
117 assert d_out.data = x"0000004100000040"
118 report "data @" & to_hstring(d_in.addr) &
119 "=" & to_hstring(d_out.data) &
120 " expected 0000004100000040"
123 wait until rising_edge(clk);
124 wait until rising_edge(clk);
125 wait until rising_edge(clk);
126 wait until rising_edge(clk);
128 assert false report "end of test" severity failure;