13 from testlib
import assertEqual
, assertNotEqual
, assertIn
, assertNotIn
14 from testlib
import assertGreater
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
, GdbSingleHartTest
, TestFailed
, assertTrue
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
, alias
):
69 a
= random
.randrange(1<<self
.hart
.xlen
)
70 b
= random
.randrange(1<<self
.hart
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
72 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
74 assertEqual(self
.gdb
.p("$%s" % name
), a
)
75 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
76 self
.gdb
.p("$%s=0x%x" % (alias
, b
))
77 assertEqual(self
.gdb
.p("$%s" % name
), b
)
79 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 assertEqual(self
.gdb
.p("$%s" % alias
), b
)
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
85 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
86 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
87 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 12))
88 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 16))
89 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
91 class SimpleS0Test(SimpleRegisterTest
):
93 self
.check_reg("s0", "x8")
95 class SimpleS1Test(SimpleRegisterTest
):
97 self
.check_reg("s1", "x9")
99 class SimpleT0Test(SimpleRegisterTest
):
101 self
.check_reg("t0", "x5")
103 class SimpleT1Test(SimpleRegisterTest
):
105 self
.check_reg("t1", "x6")
107 class SimpleF18Test(SimpleRegisterTest
):
108 def check_reg(self
, name
, alias
):
109 if self
.hart
.extensionSupported('F'):
110 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
114 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
115 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
117 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
118 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
119 self
.gdb
.p_raw("$%s=%f" % (alias
, b
))
120 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
122 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
123 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - b
), .001)
125 size
= self
.gdb
.p("sizeof($%s)" % name
)
126 if self
.hart
.extensionSupported('D'):
131 output
= self
.gdb
.p_raw("$" + name
)
132 assertEqual(output
, "void")
133 output
= self
.gdb
.p_raw("$" + alias
)
134 assertEqual(output
, "void")
137 self
.check_reg("f18", "fs2")
139 class SimpleNoExistTest(GdbTest
):
142 self
.gdb
.p("$csr2288")
143 assert False, "Reading csr2288 should have failed"
144 except testlib
.CouldNotFetch
:
147 self
.gdb
.p("$csr2288=5")
148 assert False, "Writing csr2288 should have failed"
149 except testlib
.CouldNotFetch
:
152 class SimpleMemoryTest(GdbTest
):
153 def access_test(self
, size
, data_type
):
154 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
155 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
156 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
157 addrA
= self
.hart
.ram
158 addrB
= self
.hart
.ram
+ self
.hart
.ram_size
- size
159 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrA
, a
))
160 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrB
, b
))
161 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrA
)), a
)
162 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrB
)), b
)
164 class MemTest8(SimpleMemoryTest
):
166 self
.access_test(1, 'char')
168 class MemTest16(SimpleMemoryTest
):
170 self
.access_test(2, 'short')
172 class MemTest32(SimpleMemoryTest
):
174 self
.access_test(4, 'int')
176 class MemTest64(SimpleMemoryTest
):
178 self
.access_test(8, 'long long')
180 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
181 #class MemTestReadInvalid(SimpleMemoryTest):
183 # # This test relies on 'gdb_report_data_abort enable' being executed in
184 # # the openocd.cfg file.
186 # self.gdb.p("*((int*)0xdeadbeef)")
187 # assert False, "Read should have failed."
188 # except testlib.CannotAccess as e:
189 # assertEqual(e.address, 0xdeadbeef)
190 # self.gdb.p("*((int*)0x%x)" % self.hart.ram)
192 #class MemTestWriteInvalid(SimpleMemoryTest):
194 # # This test relies on 'gdb_report_data_abort enable' being executed in
195 # # the openocd.cfg file.
197 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
198 # assert False, "Write should have failed."
199 # except testlib.CannotAccess as e:
200 # assertEqual(e.address, 0xdeadbeef)
201 # self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
203 class MemTestBlock(GdbTest
):
208 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
210 for i
in range(self
.length
/ self
.line_length
):
211 line_data
= "".join(["%c" % random
.randrange(256)
212 for _
in range(self
.line_length
)])
214 a
.write(ihex_line(i
* self
.line_length
, 0, line_data
))
217 self
.gdb
.command("shell cat %s" % a
.name
)
218 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.hart
.ram
))
220 for offset
in range(0, self
.length
, increment
) + [self
.length
-4]:
221 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.hart
.ram
+ offset
))
222 written
= ord(data
[offset
]) | \
223 (ord(data
[offset
+1]) << 8) | \
224 (ord(data
[offset
+2]) << 16) | \
225 (ord(data
[offset
+3]) << 24)
226 assertEqual(value
, written
)
228 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
229 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
230 self
.hart
.ram
, self
.hart
.ram
+ self
.length
))
231 self
.gdb
.command("shell cat %s" % b
.name
)
232 for line
in b
.xreadlines():
233 record_type
, address
, line_data
= ihex_parse(line
)
235 written_data
= data
[address
:address
+len(line_data
)]
236 if line_data
!= written_data
:
238 "Data mismatch at 0x%x; wrote %s but read %s" % (
239 address
, readable_binary_string(written_data
),
240 readable_binary_string(line_data
)))
242 class InstantHaltTest(GdbTest
):
244 """Assert that reset is really resetting what it should."""
245 self
.gdb
.command("monitor reset halt")
246 self
.gdb
.command("flushregs")
247 threads
= self
.gdb
.threads()
251 pcs
.append(self
.gdb
.p("$pc"))
253 assertIn(pc
, self
.hart
.reset_vectors
)
254 # mcycle and minstret have no defined reset value.
255 mstatus
= self
.gdb
.p("$mstatus")
256 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
259 class InstantChangePc(GdbTest
):
261 """Change the PC right as we come out of reset."""
263 self
.gdb
.command("monitor reset halt")
264 self
.gdb
.command("flushregs")
265 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
266 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
267 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
268 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
270 assertEqual((self
.hart
.ram
+ 4), self
.gdb
.p("$pc"))
272 assertEqual((self
.hart
.ram
+ 8), self
.gdb
.p("$pc"))
274 class DebugTest(GdbSingleHartTest
):
275 # Include malloc so that gdb can make function calls. I suspect this malloc
276 # will silently blow through the memory set aside for it, so be careful.
277 compile_args
= ("programs/debug.c", "programs/checksum.c",
278 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
284 def exit(self
, expected_result
=0xc86455d4):
285 output
= self
.gdb
.c()
286 assertIn("Breakpoint", output
)
287 assertIn("_exit", output
)
288 assertEqual(self
.gdb
.p("status"), expected_result
)
290 class DebugCompareSections(DebugTest
):
292 output
= self
.gdb
.command("compare-sections")
294 for line
in output
.splitlines():
295 if line
.startswith("Section"):
296 assert line
.endswith("matched.")
298 assertGreater(matched
, 1)
300 class DebugFunctionCall(DebugTest
):
302 self
.gdb
.b("main:start")
304 assertEqual(self
.gdb
.p('fib(6)'), 8)
305 assertEqual(self
.gdb
.p('fib(7)'), 13)
308 class DebugChangeString(DebugTest
):
310 text
= "This little piggy went to the market."
311 self
.gdb
.b("main:start")
313 self
.gdb
.p('fox = "%s"' % text
)
314 self
.exit(0x43b497b8)
316 class DebugTurbostep(DebugTest
):
318 """Single step a bunch of times."""
319 self
.gdb
.b("main:start")
321 self
.gdb
.command("p i=0")
327 pc
= self
.gdb
.p("$pc")
328 assertNotEqual(last_pc
, pc
)
329 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
334 # Some basic sanity that we're not running between breakpoints or
336 assertGreater(jumps
, 1)
337 assertGreater(advances
, 5)
339 class DebugExit(DebugTest
):
343 class DebugSymbols(DebugTest
):
347 output
= self
.gdb
.c()
348 assertIn(", main ", output
)
349 output
= self
.gdb
.c()
350 assertIn(", rot13 ", output
)
352 class DebugBreakpoint(DebugTest
):
355 # The breakpoint should be hit exactly 2 times.
357 output
= self
.gdb
.c()
359 assertIn("Breakpoint ", output
)
360 assertIn("rot13 ", output
)
363 class Hwbp1(DebugTest
):
365 if self
.hart
.instruction_hardware_breakpoint_count
< 1:
366 return 'not_applicable'
368 if not self
.hart
.honors_tdata1_hmode
:
369 # Run to main before setting the breakpoint, because startup code
370 # will otherwise clear the trigger that we set.
374 self
.gdb
.hbreak("rot13")
375 # The breakpoint should be hit exactly 2 times.
377 output
= self
.gdb
.c()
379 assertRegexpMatches(output
, r
"[bB]reakpoint")
380 assertIn("rot13 ", output
)
383 class Hwbp2(DebugTest
):
385 if self
.hart
.instruction_hardware_breakpoint_count
< 2:
386 return 'not_applicable'
388 self
.gdb
.hbreak("main")
389 self
.gdb
.hbreak("rot13")
390 # We should hit 3 breakpoints.
391 for expected
in ("main", "rot13", "rot13"):
392 output
= self
.gdb
.c()
394 assertRegexpMatches(output
, r
"[bB]reakpoint")
395 assertIn("%s " % expected
, output
)
398 class TooManyHwbp(DebugTest
):
401 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
403 output
= self
.gdb
.c()
404 assertIn("Cannot insert hardware breakpoint", output
)
405 # Clean up, otherwise the hardware breakpoints stay set and future
407 self
.gdb
.command("D")
409 class Registers(DebugTest
):
411 # Get to a point in the code where some registers have actually been
416 # Try both forms to test gdb.
417 for cmd
in ("info all-registers", "info registers all"):
418 output
= self
.gdb
.command(cmd
)
419 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
420 assertIn(reg
, output
)
421 for line
in output
.splitlines():
422 assertRegexpMatches(line
, r
"^\S")
425 # mcpuid is one of the few registers that should have the high bit set
427 # Leave this commented out until gdb and spike agree on the encoding of
428 # mcpuid (which is going to be renamed to misa in any case).
429 #assertRegexpMatches(output, ".*mcpuid *0x80")
432 # The instret register should always be changing.
435 # instret = self.gdb.p("$instret")
436 # assertNotEqual(instret, last_instret)
437 # last_instret = instret
442 class UserInterrupt(DebugTest
):
444 """Sending gdb ^C while the program is running should cause it to
446 self
.gdb
.b("main:start")
449 self
.gdb
.c(wait
=False)
451 output
= self
.gdb
.interrupt()
452 assert "main" in output
453 assertGreater(self
.gdb
.p("j"), 10)
457 class InterruptTest(GdbSingleHartTest
):
458 compile_args
= ("programs/interrupt.c",)
460 def early_applicable(self
):
461 return self
.target
.supports_clint_mtime
468 output
= self
.gdb
.c()
469 assertIn(" main ", output
)
470 self
.gdb
.b("trap_entry")
471 output
= self
.gdb
.c()
472 assertIn(" trap_entry ", output
)
473 assertEqual(self
.gdb
.p("$mip") & 0x80, 0x80)
474 assertEqual(self
.gdb
.p("interrupt_count"), 0)
475 # You'd expect local to still be 0, but it looks like spike doesn't
476 # jump to the interrupt handler immediately after the write to
478 assertLess(self
.gdb
.p("local"), 1000)
479 self
.gdb
.command("delete breakpoints")
481 self
.gdb
.c(wait
=False)
484 interrupt_count
= self
.gdb
.p("interrupt_count")
485 local
= self
.gdb
.p("local")
486 if interrupt_count
> 1000 and \
490 assertGreater(interrupt_count
, 1000)
491 assertGreater(local
, 1000)
493 def postMortem(self
):
494 GdbSingleHartTest
.postMortem(self
)
495 self
.gdb
.p("*((long long*) 0x200bff8)")
496 self
.gdb
.p("*((long long*) 0x2004000)")
497 self
.gdb
.p("interrupt_count")
500 class MulticoreRegTest(GdbTest
):
501 compile_args
= ("programs/infinite_loop.S", "-DMULTICORE")
503 def early_applicable(self
):
504 return len(self
.target
.harts
) > 1
508 for hart
in self
.target
.harts
:
509 self
.gdb
.select_hart(hart
)
510 self
.gdb
.p("$pc=_start")
514 for hart
in self
.target
.harts
:
515 self
.gdb
.select_hart(hart
)
518 assertIn("main", self
.gdb
.where())
519 self
.gdb
.command("delete breakpoints")
521 # Run through the entire loop.
522 for hart
in self
.target
.harts
:
523 self
.gdb
.select_hart(hart
)
524 self
.gdb
.b("main_end")
526 assertIn("main_end", self
.gdb
.where())
529 for hart
in self
.target
.harts
:
530 self
.gdb
.select_hart(hart
)
531 # Check register values.
532 hart_id
= self
.gdb
.p("$x1")
533 assertNotIn(hart_id
, hart_ids
)
534 hart_ids
.append(hart_id
)
535 for n
in range(2, 32):
536 value
= self
.gdb
.p("$x%d" % n
)
537 assertEqual(value
, hart_ids
[-1] + n
- 1)
539 # Confirmed that we read different register values for different harts.
540 # Write a new value to x1, and run through the add sequence again.
542 for hart
in self
.target
.harts
:
543 self
.gdb
.select_hart(hart
)
544 self
.gdb
.p("$x1=0x%x" % (hart
.index
* 0x800))
545 self
.gdb
.p("$pc=main_post_csrr")
547 for hart
in self
.target
.harts
:
548 self
.gdb
.select_hart(hart
)
549 assertIn("main", self
.gdb
.where())
550 # Check register values.
551 for n
in range(1, 32):
552 value
= self
.gdb
.p("$x%d" % n
)
553 assertEqual(value
, hart
.index
* 0x800 + n
- 1)
555 class MulticoreRunHaltStepiTest(GdbTest
):
556 compile_args
= ("programs/multicore.c", "-DMULTICORE")
558 def early_applicable(self
):
559 return len(self
.target
.harts
) > 1
563 for hart
in self
.target
.harts
:
564 self
.gdb
.select_hart(hart
)
565 self
.gdb
.p("$mhartid")
566 self
.gdb
.p("$pc=_start")
569 previous_hart_count
= [0 for h
in self
.target
.harts
]
570 previous_interrupt_count
= [0 for h
in self
.target
.harts
]
573 # 3 attempts for each time we want the check to pass
574 for attempt
in range(3):
575 self
.gdb
.global_command("echo round %d attempt %d\\n" % (i
,
577 self
.gdb
.c_all(wait
=False)
579 self
.gdb
.interrupt_all()
580 hart_count
= self
.gdb
.p("hart_count")
581 interrupt_count
= self
.gdb
.p("interrupt_count")
583 for i
, h
in enumerate(self
.target
.harts
):
584 if hart_count
[i
] <= previous_hart_count
[i
]:
587 if interrupt_count
[i
] <= previous_interrupt_count
[i
]:
592 self
.gdb
.p("$mstatus")
594 self
.gdb
.p("buf", fmt
="")
595 self
.gdb
.select_hart(h
)
596 pc
= self
.gdb
.p("$pc")
598 stepped_pc
= self
.gdb
.p("$pc")
599 assertNotEqual(pc
, stepped_pc
)
600 previous_hart_count
= hart_count
601 previous_interrupt_count
= interrupt_count
606 "hart count or interrupt didn't increment as expected"
608 class MulticoreRunAllHaltOne(GdbTest
):
609 compile_args
= ("programs/multicore.c", "-DMULTICORE")
611 def early_applicable(self
):
612 return len(self
.target
.harts
) > 1
615 self
.gdb
.select_hart(self
.target
.harts
[0])
617 for hart
in self
.target
.harts
:
618 self
.gdb
.select_hart(hart
)
619 self
.gdb
.p("$pc=_start")
622 if not self
.gdb
.one_hart_per_gdb():
623 return 'not_applicable'
625 # Run harts in reverse order
626 for h
in reversed(self
.target
.harts
):
627 self
.gdb
.select_hart(h
)
628 self
.gdb
.c(wait
=False)
631 # Give OpenOCD time to call poll() on both harts, which is what causes
634 self
.gdb
.p("buf", fmt
="")
636 class StepTest(GdbSingleHartTest
):
637 compile_args
= ("programs/step.S", )
645 main_address
= self
.gdb
.p("$pc")
646 if self
.hart
.extensionSupported("c"):
647 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
649 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
650 for expected
in sequence
:
652 pc
= self
.gdb
.p("$pc")
653 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
655 class TriggerTest(GdbSingleHartTest
):
656 compile_args
= ("programs/trigger.S", )
664 output
= self
.gdb
.c()
665 assertIn("Breakpoint", output
)
666 assertIn("_exit", output
)
668 class TriggerExecuteInstant(TriggerTest
):
669 """Test an execute breakpoint on the first instruction executed out of
672 main_address
= self
.gdb
.p("$pc")
673 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
675 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
677 # FIXME: Triggers aren't quite working yet
678 #class TriggerLoadAddress(TriggerTest):
680 # self.gdb.command("rwatch *((&data)+1)")
681 # output = self.gdb.c()
682 # assertIn("read_loop", output)
683 # assertEqual(self.gdb.p("$a0"),
684 # self.gdb.p("(&data)+1"))
687 class TriggerLoadAddressInstant(TriggerTest
):
688 """Test a load address breakpoint on the first instruction executed out of
691 self
.gdb
.command("b just_before_read_loop")
693 read_loop
= self
.gdb
.p("&read_loop")
694 read_again
= self
.gdb
.p("&read_again")
695 self
.gdb
.command("rwatch data")
697 # Accept hitting the breakpoint before or after the load instruction.
698 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
699 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
702 assertIn(self
.gdb
.p("$pc"), [read_again
, read_again
+ 4])
703 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
705 # FIXME: Triggers aren't quite working yet
706 #class TriggerStoreAddress(TriggerTest):
708 # self.gdb.command("watch *((&data)+3)")
709 # output = self.gdb.c()
710 # assertIn("write_loop", output)
711 # assertEqual(self.gdb.p("$a0"),
712 # self.gdb.p("(&data)+3"))
715 class TriggerStoreAddressInstant(TriggerTest
):
717 """Test a store address breakpoint on the first instruction executed out
719 self
.gdb
.command("b just_before_write_loop")
721 write_loop
= self
.gdb
.p("&write_loop")
722 self
.gdb
.command("watch data")
724 # Accept hitting the breakpoint before or after the store instruction.
725 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
726 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
728 class TriggerDmode(TriggerTest
):
729 def early_applicable(self
):
730 return self
.hart
.honors_tdata1_hmode
732 def check_triggers(self
, tdata1_lsbs
, tdata2
):
733 dmode
= 1 << (self
.hart
.xlen
-5)
737 if self
.hart
.xlen
== 32:
739 elif self
.hart
.xlen
== 64:
740 xlen_type
= 'long long'
742 raise NotImplementedError
747 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
750 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
755 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
756 assertEqual(tdata2
, tdata2
)
759 assertEqual(dmode_count
, 1)
764 self
.gdb
.command("hbreak write_load_trigger")
765 self
.gdb
.b("clear_triggers")
766 self
.gdb
.p("$pc=write_store_trigger")
767 output
= self
.gdb
.c()
768 assertIn("write_load_trigger", output
)
769 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
770 output
= self
.gdb
.c()
771 assertIn("clear_triggers", output
)
772 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
774 class RegsTest(GdbSingleHartTest
):
775 compile_args
= ("programs/regs.S", )
779 self
.gdb
.b("handle_trap")
782 class WriteGprs(RegsTest
):
784 regs
= [("x%d" % n
) for n
in range(2, 32)]
786 self
.gdb
.p("$pc=write_regs")
787 for i
, r
in enumerate(regs
):
788 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
789 self
.gdb
.p("$x1=data")
790 self
.gdb
.command("b all_done")
791 output
= self
.gdb
.c()
792 assertIn("Breakpoint ", output
)
794 # Just to get this data in the log.
795 self
.gdb
.command("x/30gx data")
796 self
.gdb
.command("info registers")
797 for n
in range(len(regs
)):
798 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
799 ((0xdeadbeef<<n
)+17) & ((1<<self
.hart
.xlen
)-1))
801 class WriteCsrs(RegsTest
):
803 # As much a test of gdb as of the simulator.
804 self
.gdb
.p("$mscratch=0")
806 assertEqual(self
.gdb
.p("$mscratch"), 0)
807 self
.gdb
.p("$mscratch=123")
809 assertEqual(self
.gdb
.p("$mscratch"), 123)
811 self
.gdb
.p("$pc=write_regs")
812 self
.gdb
.p("$x1=data")
813 self
.gdb
.command("b all_done")
814 self
.gdb
.command("c")
816 assertEqual(123, self
.gdb
.p("$mscratch"))
817 assertEqual(123, self
.gdb
.p("$x1"))
818 assertEqual(123, self
.gdb
.p("$csr832"))
820 class DownloadTest(GdbTest
):
822 # pylint: disable=attribute-defined-outside-init
823 length
= min(2**10, self
.hart
.ram_size
- 2048)
824 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
825 suffix
=".c", delete
=False)
826 self
.download_c
.write("#include <stdint.h>\n")
827 self
.download_c
.write(
828 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
829 self
.download_c
.write("uint32_t length = %d;\n" % length
)
830 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
832 assert length
% 16 == 0
833 for i
in range(length
/ 16):
834 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
836 value
= random
.randrange(1<<8)
837 self
.download_c
.write("0x%02x, " % value
)
838 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
839 self
.download_c
.write("\n")
840 self
.download_c
.write("};\n")
841 self
.download_c
.write("uint8_t *data = &d[0];\n")
842 self
.download_c
.write(
843 "uint32_t main() { return crc32a(data, length); }\n")
844 self
.download_c
.flush()
849 self
.binary
= self
.target
.compile(self
.hart
, self
.download_c
.name
,
850 "programs/checksum.c")
851 self
.gdb
.global_command("file %s" % self
.binary
)
855 self
.parkOtherHarts()
856 self
.gdb
.command("b _exit")
858 assertEqual(self
.gdb
.p("status"), self
.crc
)
859 os
.unlink(self
.download_c
.name
)
861 #class MprvTest(GdbSingleHartTest):
862 # compile_args = ("programs/mprv.S", )
867 # """Test that the debugger can access memory when MPRV is set."""
868 # self.gdb.c(wait=False)
870 # self.gdb.interrupt()
871 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
872 # assertIn("0xbead", output)
874 class PrivTest(GdbSingleHartTest
):
875 compile_args
= ("programs/priv.S", )
877 # pylint: disable=attribute-defined-outside-init
880 misa
= self
.hart
.misa
881 self
.supported
= set()
883 self
.supported
.add(0)
885 self
.supported
.add(1)
887 self
.supported
.add(2)
888 self
.supported
.add(3)
890 class PrivRw(PrivTest
):
892 """Test reading/writing priv."""
893 # Disable physical memory protection by allowing U mode access to all
896 self
.gdb
.p("$pmpcfg0=0xf") # TOR, R, W, X
897 self
.gdb
.p("$pmpaddr0=0x%x" %
898 ((self
.hart
.ram
+ self
.hart
.ram_size
) >> 2))
899 except testlib
.CouldNotFetch
:
900 # PMP registers are optional
903 # Ensure Virtual Memory is disabled if applicable (SATP register is not
906 self
.gdb
.p("$satp=0")
907 except testlib
.CouldNotFetch
:
908 # SATP only exists if you have S mode.
911 # Leave the PC at _start, where the first 4 instructions should be
913 for privilege
in range(4):
914 self
.gdb
.p("$priv=%d" % privilege
)
916 actual
= self
.gdb
.p("$priv")
917 assertIn(actual
, self
.supported
)
918 if privilege
in self
.supported
:
919 assertEqual(actual
, privilege
)
921 class PrivChange(PrivTest
):
923 """Test that the core's privilege level actually changes."""
925 if 0 not in self
.supported
:
926 return 'not_applicable'
932 self
.gdb
.p("$priv=3")
933 main_address
= self
.gdb
.p("$pc")
935 assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main_address
+4))
938 self
.gdb
.p("$priv=0")
940 # Should have taken an exception, so be nowhere near main.
941 pc
= self
.gdb
.p("$pc")
942 assertTrue(pc
< main_address
or pc
> main_address
+ 0x100)
946 parser
= argparse
.ArgumentParser(
947 description
="Test that gdb can talk to a RISC-V target.",
949 Example command line from the real world:
950 Run all RegsTest cases against a physical FPGA, with custom openocd command:
951 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
953 targets
.add_target_options(parser
)
955 testlib
.add_test_run_options(parser
)
957 # TODO: remove global
958 global parsed
# pylint: disable=global-statement
959 parsed
= parser
.parse_args()
960 target
= targets
.target(parsed
)
961 testlib
.print_log_names
= parsed
.print_log_names
963 module
= sys
.modules
[__name__
]
965 return testlib
.run_all_tests(module
, target
, parsed
)
967 # TROUBLESHOOTING TIPS
968 # If a particular test fails, run just that one test, eg.:
969 # ./gdbserver.py MprvTest.test_mprv
970 # Then inspect gdb.log and spike.log to see what happened in more detail.
972 if __name__
== '__main__':