15 MSTATUS_UIE
= 0x00000001
16 MSTATUS_SIE
= 0x00000002
17 MSTATUS_HIE
= 0x00000004
18 MSTATUS_MIE
= 0x00000008
19 MSTATUS_UPIE
= 0x00000010
20 MSTATUS_SPIE
= 0x00000020
21 MSTATUS_HPIE
= 0x00000040
22 MSTATUS_MPIE
= 0x00000080
23 MSTATUS_SPP
= 0x00000100
24 MSTATUS_HPP
= 0x00000600
25 MSTATUS_MPP
= 0x00001800
26 MSTATUS_FS
= 0x00006000
27 MSTATUS_XS
= 0x00018000
28 MSTATUS_MPRV
= 0x00020000
29 MSTATUS_PUM
= 0x00040000
30 MSTATUS_MXR
= 0x00080000
31 MSTATUS_VM
= 0x1F000000
32 MSTATUS32_SD
= 0x80000000
33 MSTATUS64_SD
= 0x8000000000000000
43 gdb
= testlib
.Gdb(parsed
.gdb
)
48 gdb
.command("file %s" % binary
)
50 gdb
.command("set arch riscv:rv%d" % target
.xlen
)
51 gdb
.command("set remotetimeout %d" % target
.timeout_sec
)
53 gdb
.command("target extended-remote localhost:%d" % port
)
60 def ihex_line(address
, record_type
, data
):
61 assert len(data
) < 128
62 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
64 check
+= address
% 256
70 line
+= "%02X" % value
71 line
+= "%02X\n" % ((256-check
)%256)
75 assert line
.startswith(":")
77 data_len
= int(line
[:2], 16)
78 address
= int(line
[2:6], 16)
79 record_type
= int(line
[6:8], 16)
81 for i
in range(data_len
):
82 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
83 return record_type
, address
, data
85 def readable_binary_string(s
):
86 return "".join("%02x" % ord(c
) for c
in s
)
88 class DeleteServer(unittest
.TestCase
):
92 class SimpleRegisterTest(DeleteServer
):
94 self
.server
= target
.server()
95 self
.gdb
= gdb(target
, self
.server
.port
)
98 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
99 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
100 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
101 self
.gdb
.p("$pc=0x%x" % target
.ram
)
103 def check_reg(self
, name
):
104 a
= random
.randrange(1<<target
.xlen
)
105 b
= random
.randrange(1<<target
.xlen
)
106 self
.gdb
.p("$%s=0x%x" % (name
, a
))
108 self
.assertEqual(self
.gdb
.p("$%s" % name
), a
)
109 self
.gdb
.p("$%s=0x%x" % (name
, b
))
111 self
.assertEqual(self
.gdb
.p("$%s" % name
), b
)
114 # S0 is saved/restored in DSCRATCH
118 # S1 is saved/restored in Debug RAM
122 # T0 is not saved/restored at all
126 # T2 is not saved/restored at all
129 class SimpleMemoryTest(DeleteServer
):
131 self
.server
= target
.server()
132 self
.gdb
= gdb(target
, self
.server
.port
)
134 def access_test(self
, size
, data_type
):
135 self
.assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
),
137 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
138 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
139 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
, a
))
140 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
+ size
, b
))
141 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
)), a
)
142 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
+ size
)), b
)
145 self
.access_test(1, 'char')
148 self
.access_test(2, 'short')
151 self
.access_test(4, 'int')
154 self
.access_test(8, 'long long')
156 def test_block(self
):
159 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
161 for i
in range(length
/ line_length
):
162 line_data
= "".join(["%c" % random
.randrange(256) for _
in range(line_length
)])
164 a
.write(ihex_line(i
* line_length
, 0, line_data
))
167 self
.gdb
.command("restore %s 0x%x" % (a
.name
, target
.ram
))
168 for offset
in range(0, length
, 19*4) + [length
-4]:
169 value
= self
.gdb
.p("*((int*)0x%x)" % (target
.ram
+ offset
))
170 written
= ord(data
[offset
]) | \
171 (ord(data
[offset
+1]) << 8) | \
172 (ord(data
[offset
+2]) << 16) | \
173 (ord(data
[offset
+3]) << 24)
174 self
.assertEqual(value
, written
)
176 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
177 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
, target
.ram
,
178 target
.ram
+ length
))
180 record_type
, address
, line_data
= ihex_parse(line
)
181 if (record_type
== 0):
182 self
.assertEqual(readable_binary_string(line_data
),
183 readable_binary_string(data
[address
:address
+len(line_data
)]))
185 class InstantHaltTest(DeleteServer
):
187 self
.server
= target
.server()
188 self
.gdb
= gdb(target
, self
.server
.port
)
190 def test_instant_halt(self
):
191 self
.assertEqual(target
.reset_vector
, self
.gdb
.p("$pc"))
192 # mcycle and minstret have no defined reset value.
193 mstatus
= self
.gdb
.p("$mstatus")
194 self
.assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
197 def test_change_pc(self
):
198 """Change the PC right as we come out of reset."""
200 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
201 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
202 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
203 self
.gdb
.p("$pc=0x%x" % target
.ram
)
205 self
.assertEqual((target
.ram
+ 4), self
.gdb
.p("$pc"))
207 self
.assertEqual((target
.ram
+ 8), self
.gdb
.p("$pc"))
209 class DebugTest(DeleteServer
):
211 # Include malloc so that gdb can make function calls. I suspect this
212 # malloc will silently blow through the memory set aside for it, so be
214 self
.binary
= target
.compile("programs/debug.c", "programs/checksum.c",
215 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
216 self
.server
= target
.server()
217 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
221 def exit(self
, expected_result
= 0xc86455d4):
222 output
= self
.gdb
.c()
223 self
.assertIn("Breakpoint", output
)
224 self
.assertIn("_exit", output
)
225 self
.assertEqual(self
.gdb
.p("status"), expected_result
)
227 def test_function_call(self
):
228 self
.gdb
.b("main:start")
230 self
.assertEqual(self
.gdb
.p('fib(6)'), 8)
231 self
.assertEqual(self
.gdb
.p('fib(7)'), 13)
234 def test_change_string(self
):
235 text
= "This little piggy went to the market."
236 self
.gdb
.b("main:start")
238 self
.gdb
.p('fox = "%s"' % text
)
239 self
.exit(0x43b497b8)
241 def test_turbostep(self
):
242 """Single step a bunch of times."""
243 self
.gdb
.b("main:start")
245 self
.gdb
.command("p i=0");
251 pc
= self
.gdb
.p("$pc")
252 self
.assertNotEqual(last_pc
, pc
)
253 if (last_pc
and pc
> last_pc
and pc
- last_pc
<= 4):
258 # Some basic sanity that we're not running between breakpoints or
260 self
.assertGreater(jumps
, 10)
261 self
.assertGreater(advances
, 50)
266 def test_symbols(self
):
269 output
= self
.gdb
.c()
270 self
.assertIn(", main ", output
)
271 output
= self
.gdb
.c()
272 self
.assertIn(", rot13 ", output
)
274 def test_breakpoint(self
):
276 # The breakpoint should be hit exactly 2 times.
278 output
= self
.gdb
.c()
280 self
.assertIn("Breakpoint ", output
)
281 #TODO self.assertIn("rot13 ", output)
284 def test_hwbp_1(self
):
285 if target
.instruction_hardware_breakpoint_count
< 1:
288 self
.gdb
.hbreak("rot13")
289 # The breakpoint should be hit exactly 2 times.
291 output
= self
.gdb
.c()
293 self
.assertIn("Breakpoint ", output
)
294 #TODO self.assertIn("rot13 ", output)
297 def test_hwbp_2(self
):
298 if target
.instruction_hardware_breakpoint_count
< 2:
301 self
.gdb
.hbreak("main")
302 self
.gdb
.hbreak("rot13")
303 # We should hit 3 breakpoints.
305 output
= self
.gdb
.c()
307 self
.assertIn("Breakpoint ", output
)
308 #TODO self.assertIn("rot13 ", output)
311 def test_too_many_hwbp(self
):
313 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
315 output
= self
.gdb
.c()
316 self
.assertIn("Cannot insert hardware breakpoint", output
)
317 # Clean up, otherwise the hardware breakpoints stay set and future
319 self
.gdb
.command("D")
321 def test_registers(self
):
322 # Get to a point in the code where some registers have actually been
327 # Try both forms to test gdb.
328 for cmd
in ("info all-registers", "info registers all"):
329 output
= self
.gdb
.command(cmd
)
330 self
.assertNotIn("Could not", output
)
331 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
332 self
.assertIn(reg
, output
)
335 # mcpuid is one of the few registers that should have the high bit set
337 # Leave this commented out until gdb and spike agree on the encoding of
338 # mcpuid (which is going to be renamed to misa in any case).
339 #self.assertRegexpMatches(output, ".*mcpuid *0x80")
342 # The instret register should always be changing.
345 # instret = self.gdb.p("$instret")
346 # self.assertNotEqual(instret, last_instret)
347 # last_instret = instret
352 def test_interrupt(self
):
353 """Sending gdb ^C while the program is running should cause it to halt."""
354 self
.gdb
.b("main:start")
357 self
.gdb
.c(wait
=False)
359 output
= self
.gdb
.interrupt()
360 #TODO: assert "main" in output
361 self
.assertGreater(self
.gdb
.p("j"), 10)
365 class StepTest(DeleteServer
):
367 self
.binary
= target
.compile("programs/step.S")
368 self
.server
= target
.server()
369 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
375 main
= self
.gdb
.p("$pc")
376 for expected
in (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c):
378 pc
= self
.gdb
.p("$pc")
379 self
.assertEqual("%x" % pc
, "%x" % (expected
+ main
))
381 class TriggerTest(DeleteServer
):
383 self
.binary
= target
.compile("programs/trigger.S")
384 self
.server
= target
.server()
385 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
392 output
= self
.gdb
.c()
393 self
.assertIn("Breakpoint", output
)
394 self
.assertIn("_exit", output
)
396 def test_execute_immediate(self
):
397 """Test an execute breakpoint on the first instruction executed out of
399 main
= self
.gdb
.p("$pc")
400 self
.gdb
.command("hbreak *0x%x" % (main
+ 4))
402 self
.assertEqual(self
.gdb
.p("$pc"), main
+4)
404 def test_load_address(self
):
405 self
.gdb
.command("rwatch *((&data)+1)");
406 output
= self
.gdb
.c()
407 self
.assertIn("read_loop", output
)
408 self
.assertEqual(self
.gdb
.p("$a0"),
409 self
.gdb
.p("(&data)+1"))
412 def test_load_address_immediate(self
):
413 """Test a load address breakpoint on the first instruction executed out
415 write_loop
= self
.gdb
.p("&write_loop")
416 self
.gdb
.command("rwatch data");
418 self
.assertEqual(self
.gdb
.p("$pc"), write_loop
)
419 self
.assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("(&data)+1"))
421 def test_store_address(self
):
422 self
.gdb
.command("watch *((&data)+3)");
423 output
= self
.gdb
.c()
424 self
.assertIn("write_loop", output
)
425 self
.assertEqual(self
.gdb
.p("$a0"),
426 self
.gdb
.p("(&data)+3"))
429 def test_dmode(self
):
430 self
.gdb
.command("hbreak handle_trap")
431 self
.gdb
.p("$pc=write_valid")
432 output
= self
.gdb
.c()
433 self
.assertIn("handle_trap", output
)
434 self
.assertIn("mcause=2", output
)
435 self
.assertIn("mepc=%d" % self
.gdb
.p("&write_invalid_illegal"), output
)
437 class RegsTest(DeleteServer
):
439 self
.binary
= target
.compile("programs/regs.S")
440 self
.server
= target
.server()
441 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
444 self
.gdb
.b("handle_trap")
447 def test_write_gprs(self
):
448 regs
= [("x%d" % n
) for n
in range(2, 32)]
450 self
.gdb
.p("$pc=write_regs")
451 for i
, r
in enumerate(regs
):
452 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
453 self
.gdb
.p("$x1=data")
454 self
.gdb
.command("b all_done")
455 output
= self
.gdb
.c()
456 self
.assertIn("Breakpoint ", output
)
458 # Just to get this data in the log.
459 self
.gdb
.command("x/30gx data")
460 self
.gdb
.command("info registers")
461 for n
in range(len(regs
)):
462 self
.assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
463 ((0xdeadbeef<<n
)+17) & ((1<<target
.xlen
)-1))
465 def test_write_csrs(self
):
466 # As much a test of gdb as of the simulator.
467 self
.gdb
.p("$mscratch=0")
469 self
.assertEqual(self
.gdb
.p("$mscratch"), 0)
470 self
.gdb
.p("$mscratch=123")
472 self
.assertEqual(self
.gdb
.p("$mscratch"), 123)
474 self
.gdb
.command("p $pc=write_regs")
475 self
.gdb
.command("p $a0=data")
476 self
.gdb
.command("b all_done")
477 self
.gdb
.command("c")
479 self
.assertEqual(123, self
.gdb
.p("$mscratch"))
480 self
.assertEqual(123, self
.gdb
.p("$x1"))
481 self
.assertEqual(123, self
.gdb
.p("$csr832"))
483 class DownloadTest(DeleteServer
):
485 length
= min(2**20, target
.ram_size
- 2048)
486 download_c
= tempfile
.NamedTemporaryFile(prefix
="download_", suffix
=".c")
487 download_c
.write("#include <stdint.h>\n")
488 download_c
.write("unsigned int crc32a(uint8_t *message, unsigned int size);\n")
489 download_c
.write("uint32_t length = %d;\n" % length
)
490 download_c
.write("uint8_t d[%d] = {\n" % length
)
492 for i
in range(length
/ 16):
493 download_c
.write(" /* 0x%04x */ " % (i
* 16));
495 value
= random
.randrange(1<<8)
496 download_c
.write("%d, " % value
)
497 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
498 download_c
.write("\n");
499 download_c
.write("};\n");
500 download_c
.write("uint8_t *data = &d[0];\n");
501 download_c
.write("uint32_t main() { return crc32a(data, length); }\n")
507 self
.binary
= target
.compile(download_c
.name
, "programs/checksum.c")
508 self
.server
= target
.server()
509 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
511 def test_download(self
):
512 output
= self
.gdb
.load()
513 self
.gdb
.command("b _exit")
515 self
.assertEqual(self
.gdb
.p("status"), self
.crc
)
517 class MprvTest(DeleteServer
):
519 self
.binary
= target
.compile("programs/mprv.S")
520 self
.server
= target
.server()
521 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
525 """Test that the debugger can access memory when MPRV is set."""
526 self
.gdb
.c(wait
=False)
529 output
= self
.gdb
.command("p/x *(int*)(((char*)&data)-0x80000000)")
530 self
.assertIn("0xbead", output
)
532 class PrivTest(DeleteServer
):
534 self
.binary
= target
.compile("programs/priv.S")
535 self
.server
= target
.server()
536 self
.gdb
= gdb(target
, self
.server
.port
, self
.binary
)
539 misa
= self
.gdb
.p("$misa")
540 self
.supported
= set()
542 self
.supported
.add(0)
544 self
.supported
.add(1)
546 self
.supported
.add(2)
547 self
.supported
.add(3)
550 """Test reading/writing priv."""
551 for privilege
in range(4):
552 self
.gdb
.p("$priv=%d" % privilege
)
554 actual
= self
.gdb
.p("$priv")
555 self
.assertIn(actual
, self
.supported
)
556 if privilege
in self
.supported
:
557 self
.assertEqual(actual
, privilege
)
559 def test_change(self
):
560 """Test that the core's privilege level actually changes."""
562 if 0 not in self
.supported
:
563 # TODO: return not applicable
570 self
.gdb
.p("$priv=3")
571 main
= self
.gdb
.p("$pc")
573 self
.assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main
+4))
576 self
.gdb
.p("$priv=0")
578 # Should have taken an exception, so be nowhere near main.
579 pc
= self
.gdb
.p("$pc")
580 self
.assertTrue(pc
< main
or pc
> main
+ 0x100)
582 class Target(object):
587 raise NotImplementedError
589 def compile(self
, *sources
):
590 binary_name
= "%s_%s-%d" % (
592 os
.path
.basename(os
.path
.splitext(sources
[0])[0]),
595 self
.temporary_binary
= tempfile
.NamedTemporaryFile(
596 prefix
=binary_name
+ "_")
597 binary_name
= self
.temporary_binary
.name
598 testlib
.compile(sources
+
599 ("programs/entry.S", "programs/init.c",
601 "-T", "targets/%s/link.lds" % (self
.directory
or self
.name
),
608 class SpikeTarget(Target
):
611 ram_size
= 5 * 1024 * 1024
612 instruction_hardware_breakpoint_count
= 4
613 reset_vector
= 0x1000
615 class Spike64Target(SpikeTarget
):
620 return testlib
.Spike(parsed
.cmd
, halted
=True)
622 class Spike32Target(SpikeTarget
):
627 return testlib
.Spike(parsed
.cmd
, halted
=True, xlen
=32)
629 class FreedomE300Target(Target
):
630 name
= "freedom-e300"
634 instruction_hardware_breakpoint_count
= 2
637 return testlib
.Openocd(cmd
=parsed
.cmd
,
638 config
="targets/%s/openocd.cfg" % self
.name
)
640 class FreedomE300SimTarget(Target
):
641 name
= "freedom-e300-sim"
645 ram_size
= 256 * 1024 * 1024
646 instruction_hardware_breakpoint_count
= 2
649 sim
= testlib
.VcsSim(simv
=parsed
.run
, debug
=False)
650 openocd
= testlib
.Openocd(cmd
=parsed
.cmd
,
651 config
="targets/%s/openocd.cfg" % self
.name
,
656 class FreedomU500Target(Target
):
657 name
= "freedom-u500"
661 instruction_hardware_breakpoint_count
= 2
664 return testlib
.Openocd(cmd
=parsed
.cmd
,
665 config
="targets/%s/openocd.cfg" % self
.name
)
667 class FreedomU500SimTarget(Target
):
668 name
= "freedom-u500-sim"
672 ram_size
= 256 * 1024 * 1024
673 instruction_hardware_breakpoint_count
= 2
676 sim
= testlib
.VcsSim(simv
=parsed
.run
, debug
=False)
677 openocd
= testlib
.Openocd(cmd
=parsed
.cmd
,
678 config
="targets/%s/openocd.cfg" % self
.name
,
688 FreedomE300SimTarget
,
689 FreedomU500SimTarget
]
692 parser
= argparse
.ArgumentParser(
694 Example command line from the real world:
695 Run all RegsTest cases against a physical FPGA, with custom openocd command:
696 ./gdbserver.py --freedom-e-300 --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" -- -vf RegsTest
698 group
= parser
.add_mutually_exclusive_group(required
=True)
700 group
.add_argument("--%s" % t
.name
, action
="store_const", const
=t
,
702 parser
.add_argument("--run",
703 help="The command to use to start the actual target (e.g. simulation)")
704 parser
.add_argument("--cmd",
705 help="The command to use to start the debug server.")
706 parser
.add_argument("--gdb",
707 help="The command to use to start gdb.")
709 xlen_group
= parser
.add_mutually_exclusive_group()
710 xlen_group
.add_argument("--32", action
="store_const", const
=32, dest
="xlen",
711 help="Force the target to be 32-bit.")
712 xlen_group
.add_argument("--64", action
="store_const", const
=64, dest
="xlen",
713 help="Force the target to be 64-bit.")
715 parser
.add_argument("--isolate", action
="store_true",
716 help="Try to run in such a way that multiple instances can run at "
717 "the same time. This may make it harder to debug a failure if it "
720 parser
.add_argument("unittest", nargs
="*")
722 parsed
= parser
.parse_args()
725 target
= parsed
.target()
728 target
.xlen
= parsed
.xlen
730 unittest
.main(argv
=[sys
.argv
[0]] + parsed
.unittest
)
732 # TROUBLESHOOTING TIPS
733 # If a particular test fails, run just that one test, eg.:
734 # ./gdbserver.py MprvTest.test_mprv
735 # Then inspect gdb.log and spike.log to see what happened in more detail.
737 if __name__
== '__main__':