13 from testlib
import assertEqual
, assertNotEqual
, assertIn
14 from testlib
import assertGreater
, assertTrue
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
):
69 a
= random
.randrange(1<<self
.target
.xlen
)
70 b
= random
.randrange(1<<self
.target
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
73 assertEqual(self
.gdb
.p("$%s" % name
), a
)
74 self
.gdb
.p("$%s=0x%x" % (name
, b
))
76 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.target
.ram
)
81 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 4))
82 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 8))
83 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 12))
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 16))
85 self
.gdb
.p("$pc=0x%x" % self
.target
.ram
)
87 class SimpleS0Test(SimpleRegisterTest
):
91 class SimpleS1Test(SimpleRegisterTest
):
95 class SimpleT0Test(SimpleRegisterTest
):
99 class SimpleT1Test(SimpleRegisterTest
):
103 class SimpleF18Test(SimpleRegisterTest
):
104 def check_reg(self
, name
):
105 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
109 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
111 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
112 self
.gdb
.p_raw("$%s=%f" % (name
, b
))
114 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
116 def early_applicable(self
):
117 return self
.target
.extensionSupported('F')
120 self
.check_reg("f18")
122 class SimpleMemoryTest(GdbTest
):
123 def access_test(self
, size
, data_type
):
124 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
125 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
126 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
127 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, self
.target
.ram
, a
))
128 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, self
.target
.ram
+ size
,
130 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, self
.target
.ram
)),
132 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (
133 data_type
, self
.target
.ram
+ size
)), b
)
135 class MemTest8(SimpleMemoryTest
):
137 self
.access_test(1, 'char')
139 class MemTest16(SimpleMemoryTest
):
141 self
.access_test(2, 'short')
143 class MemTest32(SimpleMemoryTest
):
145 self
.access_test(4, 'int')
147 class MemTest64(SimpleMemoryTest
):
149 self
.access_test(8, 'long long')
151 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
152 #class MemTestReadInvalid(SimpleMemoryTest):
154 # # This test relies on 'gdb_report_data_abort enable' being executed in
155 # # the openocd.cfg file.
157 # self.gdb.p("*((int*)0xdeadbeef)")
158 # assert False, "Read should have failed."
159 # except testlib.CannotAccess as e:
160 # assertEqual(e.address, 0xdeadbeef)
161 # self.gdb.p("*((int*)0x%x)" % self.target.ram)
163 #class MemTestWriteInvalid(SimpleMemoryTest):
165 # # This test relies on 'gdb_report_data_abort enable' being executed in
166 # # the openocd.cfg file.
168 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
169 # assert False, "Write should have failed."
170 # except testlib.CannotAccess as e:
171 # assertEqual(e.address, 0xdeadbeef)
172 # self.gdb.p("*((int*)0x%x)=6874742" % self.target.ram)
174 class MemTestBlock(GdbTest
):
178 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
180 for i
in range(length
/ line_length
):
181 line_data
= "".join(["%c" % random
.randrange(256)
182 for _
in range(line_length
)])
184 a
.write(ihex_line(i
* line_length
, 0, line_data
))
187 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.target
.ram
))
188 for offset
in range(0, length
, 19*4) + [length
-4]:
189 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.target
.ram
+ offset
))
190 written
= ord(data
[offset
]) | \
191 (ord(data
[offset
+1]) << 8) | \
192 (ord(data
[offset
+2]) << 16) | \
193 (ord(data
[offset
+3]) << 24)
194 assertEqual(value
, written
)
196 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
197 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
198 self
.target
.ram
, self
.target
.ram
+ length
))
200 record_type
, address
, line_data
= ihex_parse(line
)
202 assertEqual(readable_binary_string(line_data
),
203 readable_binary_string(
204 data
[address
:address
+len(line_data
)]))
206 class InstantHaltTest(GdbTest
):
208 assertEqual(self
.target
.reset_vector
, self
.gdb
.p("$pc"))
209 # mcycle and minstret have no defined reset value.
210 mstatus
= self
.gdb
.p("$mstatus")
211 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
214 class InstantChangePc(GdbTest
):
216 """Change the PC right as we come out of reset."""
218 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.target
.ram
)
219 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 4))
220 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.target
.ram
+ 8))
221 self
.gdb
.p("$pc=0x%x" % self
.target
.ram
)
223 assertEqual((self
.target
.ram
+ 4), self
.gdb
.p("$pc"))
225 assertEqual((self
.target
.ram
+ 8), self
.gdb
.p("$pc"))
227 class DebugTest(GdbTest
):
228 # Include malloc so that gdb can make function calls. I suspect this malloc
229 # will silently blow through the memory set aside for it, so be careful.
230 compile_args
= ("programs/debug.c", "programs/checksum.c",
231 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
237 def exit(self
, expected_result
=0xc86455d4):
238 output
= self
.gdb
.c()
239 assertIn("Breakpoint", output
)
240 assertIn("_exit", output
)
241 assertEqual(self
.gdb
.p("status"), expected_result
)
243 class DebugCompareSections(DebugTest
):
245 output
= self
.gdb
.command("compare-sections")
247 for line
in output
.splitlines():
248 if line
.startswith("Section"):
249 assert line
.endswith("matched.")
251 assertGreater(matched
, 1)
253 class DebugFunctionCall(DebugTest
):
255 self
.gdb
.b("main:start")
257 assertEqual(self
.gdb
.p('fib(6)'), 8)
258 assertEqual(self
.gdb
.p('fib(7)'), 13)
261 class DebugChangeString(DebugTest
):
263 text
= "This little piggy went to the market."
264 self
.gdb
.b("main:start")
266 self
.gdb
.p('fox = "%s"' % text
)
267 self
.exit(0x43b497b8)
269 class DebugTurbostep(DebugTest
):
271 """Single step a bunch of times."""
272 self
.gdb
.b("main:start")
274 self
.gdb
.command("p i=0")
280 pc
= self
.gdb
.p("$pc")
281 assertNotEqual(last_pc
, pc
)
282 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
287 # Some basic sanity that we're not running between breakpoints or
289 assertGreater(jumps
, 10)
290 assertGreater(advances
, 50)
292 class DebugExit(DebugTest
):
296 class DebugSymbols(DebugTest
):
300 output
= self
.gdb
.c()
301 assertIn(", main ", output
)
302 output
= self
.gdb
.c()
303 assertIn(", rot13 ", output
)
305 class DebugBreakpoint(DebugTest
):
308 # The breakpoint should be hit exactly 2 times.
310 output
= self
.gdb
.c()
312 assertIn("Breakpoint ", output
)
313 assertIn("rot13 ", output
)
316 class Hwbp1(DebugTest
):
318 if self
.target
.instruction_hardware_breakpoint_count
< 1:
319 return 'not_applicable'
321 self
.gdb
.hbreak("rot13")
322 # The breakpoint should be hit exactly 2 times.
324 output
= self
.gdb
.c()
326 assertRegexpMatches(output
, r
"[bB]reakpoint")
327 assertIn("rot13 ", output
)
330 class Hwbp2(DebugTest
):
332 if self
.target
.instruction_hardware_breakpoint_count
< 2:
333 return 'not_applicable'
335 self
.gdb
.hbreak("main")
336 self
.gdb
.hbreak("rot13")
337 # We should hit 3 breakpoints.
338 for expected
in ("main", "rot13", "rot13"):
339 output
= self
.gdb
.c()
341 assertRegexpMatches(output
, r
"[bB]reakpoint")
342 assertIn("%s " % expected
, output
)
345 class TooManyHwbp(DebugTest
):
348 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
350 output
= self
.gdb
.c()
351 assertIn("Cannot insert hardware breakpoint", output
)
352 # Clean up, otherwise the hardware breakpoints stay set and future
354 self
.gdb
.command("D")
356 class Registers(DebugTest
):
358 # Get to a point in the code where some registers have actually been
363 # Try both forms to test gdb.
364 for cmd
in ("info all-registers", "info registers all"):
365 output
= self
.gdb
.command(cmd
)
366 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
367 assertIn(reg
, output
)
370 # mcpuid is one of the few registers that should have the high bit set
372 # Leave this commented out until gdb and spike agree on the encoding of
373 # mcpuid (which is going to be renamed to misa in any case).
374 #assertRegexpMatches(output, ".*mcpuid *0x80")
377 # The instret register should always be changing.
380 # instret = self.gdb.p("$instret")
381 # assertNotEqual(instret, last_instret)
382 # last_instret = instret
387 class UserInterrupt(DebugTest
):
389 """Sending gdb ^C while the program is running should cause it to
391 self
.gdb
.b("main:start")
394 self
.gdb
.c(wait
=False)
396 output
= self
.gdb
.interrupt()
397 assert "main" in output
398 assertGreater(self
.gdb
.p("j"), 10)
402 class StepTest(GdbTest
):
403 compile_args
= ("programs/step.S", )
411 main_address
= self
.gdb
.p("$pc")
412 if self
.target
.extensionSupported("c"):
413 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
415 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
416 for expected
in sequence
:
418 pc
= self
.gdb
.p("$pc")
419 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
421 class TriggerTest(GdbTest
):
422 compile_args
= ("programs/trigger.S", )
430 output
= self
.gdb
.c()
431 assertIn("Breakpoint", output
)
432 assertIn("_exit", output
)
434 class TriggerExecuteInstant(TriggerTest
):
435 """Test an execute breakpoint on the first instruction executed out of
438 main_address
= self
.gdb
.p("$pc")
439 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
441 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
443 # FIXME: Triggers aren't quite working yet
444 #class TriggerLoadAddress(TriggerTest):
446 # self.gdb.command("rwatch *((&data)+1)")
447 # output = self.gdb.c()
448 # assertIn("read_loop", output)
449 # assertEqual(self.gdb.p("$a0"),
450 # self.gdb.p("(&data)+1"))
453 class TriggerLoadAddressInstant(TriggerTest
):
454 """Test a load address breakpoint on the first instruction executed out of
457 self
.gdb
.command("b just_before_read_loop")
459 read_loop
= self
.gdb
.p("&read_loop")
460 self
.gdb
.command("rwatch data")
462 # Accept hitting the breakpoint before or after the load instruction.
463 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
464 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
466 # FIXME: Triggers aren't quite working yet
467 #class TriggerStoreAddress(TriggerTest):
469 # self.gdb.command("watch *((&data)+3)")
470 # output = self.gdb.c()
471 # assertIn("write_loop", output)
472 # assertEqual(self.gdb.p("$a0"),
473 # self.gdb.p("(&data)+3"))
476 class TriggerStoreAddressInstant(TriggerTest
):
478 """Test a store address breakpoint on the first instruction executed out
480 self
.gdb
.command("b just_before_write_loop")
482 write_loop
= self
.gdb
.p("&write_loop")
483 self
.gdb
.command("watch data")
485 # Accept hitting the breakpoint before or after the store instruction.
486 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
487 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
489 class TriggerDmode(TriggerTest
):
490 def check_triggers(self
, tdata1_lsbs
, tdata2
):
491 dmode
= 1 << (self
.target
.xlen
-5)
495 if self
.target
.xlen
== 32:
497 elif self
.target
.xlen
== 64:
498 xlen_type
= 'long long'
500 raise NotImplementedError
505 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
508 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
513 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
514 assertEqual(tdata2
, tdata2
)
517 assertEqual(dmode_count
, 1)
522 self
.gdb
.command("hbreak write_load_trigger")
523 self
.gdb
.b("clear_triggers")
524 self
.gdb
.p("$pc=write_store_trigger")
525 output
= self
.gdb
.c()
526 assertIn("write_load_trigger", output
)
527 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
528 output
= self
.gdb
.c()
529 assertIn("clear_triggers", output
)
530 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
532 class RegsTest(GdbTest
):
533 compile_args
= ("programs/regs.S", )
537 self
.gdb
.b("handle_trap")
540 class WriteGprs(RegsTest
):
542 regs
= [("x%d" % n
) for n
in range(2, 32)]
544 self
.gdb
.p("$pc=write_regs")
545 for i
, r
in enumerate(regs
):
546 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
547 self
.gdb
.p("$x1=data")
548 self
.gdb
.command("b all_done")
549 output
= self
.gdb
.c()
550 assertIn("Breakpoint ", output
)
552 # Just to get this data in the log.
553 self
.gdb
.command("x/30gx data")
554 self
.gdb
.command("info registers")
555 for n
in range(len(regs
)):
556 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
557 ((0xdeadbeef<<n
)+17) & ((1<<self
.target
.xlen
)-1))
559 class WriteCsrs(RegsTest
):
561 # As much a test of gdb as of the simulator.
562 self
.gdb
.p("$mscratch=0")
564 assertEqual(self
.gdb
.p("$mscratch"), 0)
565 self
.gdb
.p("$mscratch=123")
567 assertEqual(self
.gdb
.p("$mscratch"), 123)
569 self
.gdb
.p("$pc=write_regs")
570 self
.gdb
.p("$x1=data")
571 self
.gdb
.command("b all_done")
572 self
.gdb
.command("c")
574 assertEqual(123, self
.gdb
.p("$mscratch"))
575 assertEqual(123, self
.gdb
.p("$x1"))
576 assertEqual(123, self
.gdb
.p("$csr832"))
578 class DownloadTest(GdbTest
):
580 # pylint: disable=attribute-defined-outside-init
581 length
= min(2**20, self
.target
.ram_size
- 2048)
582 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
583 suffix
=".c", delete
=False)
584 self
.download_c
.write("#include <stdint.h>\n")
585 self
.download_c
.write(
586 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
587 self
.download_c
.write("uint32_t length = %d;\n" % length
)
588 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
590 assert length
% 16 == 0
591 for i
in range(length
/ 16):
592 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
594 value
= random
.randrange(1<<8)
595 self
.download_c
.write("0x%02x, " % value
)
596 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
597 self
.download_c
.write("\n")
598 self
.download_c
.write("};\n")
599 self
.download_c
.write("uint8_t *data = &d[0];\n")
600 self
.download_c
.write(
601 "uint32_t main() { return crc32a(data, length); }\n")
602 self
.download_c
.flush()
607 self
.binary
= self
.target
.compile(self
.download_c
.name
,
608 "programs/checksum.c")
609 self
.gdb
.command("file %s" % self
.binary
)
613 self
.gdb
.command("b _exit")
614 self
.gdb
.c(timeout
=60)
615 assertEqual(self
.gdb
.p("status"), self
.crc
)
616 os
.unlink(self
.download_c
.name
)
618 # FIXME: PRIV isn't implemented in the current OpenOCD
619 #class MprvTest(GdbTest):
620 # compile_args = ("programs/mprv.S", )
625 # """Test that the debugger can access memory when MPRV is set."""
626 # self.gdb.c(wait=False)
628 # self.gdb.interrupt()
629 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
630 # assertIn("0xbead", output)
632 #class PrivTest(GdbTest):
633 # compile_args = ("programs/priv.S", )
635 # # pylint: disable=attribute-defined-outside-init
638 # misa = self.target.misa
639 # self.supported = set()
641 # self.supported.add(0)
643 # self.supported.add(1)
645 # self.supported.add(2)
646 # self.supported.add(3)
648 #class PrivRw(PrivTest):
650 # """Test reading/writing priv."""
651 # for privilege in range(4):
652 # self.gdb.p("$priv=%d" % privilege)
654 # actual = self.gdb.p("$priv")
655 # assertIn(actual, self.supported)
656 # if privilege in self.supported:
657 # assertEqual(actual, privilege)
659 #class PrivChange(PrivTest):
661 # """Test that the core's privilege level actually changes."""
663 # if 0 not in self.supported:
664 # return 'not_applicable'
670 # self.gdb.p("$priv=3")
671 # main_address = self.gdb.p("$pc")
673 # assertEqual("%x" % self.gdb.p("$pc"), "%x" % (main_address+4))
676 # self.gdb.p("$priv=0")
678 # # Should have taken an exception, so be nowhere near main.
679 # pc = self.gdb.p("$pc")
680 # assertTrue(pc < main_address or pc > main_address + 0x100)
684 parser
= argparse
.ArgumentParser(
685 description
="Test that gdb can talk to a RISC-V target.",
687 Example command line from the real world:
688 Run all RegsTest cases against a physical FPGA, with custom openocd command:
689 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
691 targets
.add_target_options(parser
)
693 testlib
.add_test_run_options(parser
)
695 # TODO: remove global
696 global parsed
# pylint: disable=global-statement
697 parsed
= parser
.parse_args()
699 target
= parsed
.target(parsed
.server_cmd
, parsed
.sim_cmd
, parsed
.isolate
)
701 target
.xlen
= parsed
.xlen
703 module
= sys
.modules
[__name__
]
705 return testlib
.run_all_tests(module
, target
, parsed
)
707 # TROUBLESHOOTING TIPS
708 # If a particular test fails, run just that one test, eg.:
709 # ./gdbserver.py MprvTest.test_mprv
710 # Then inspect gdb.log and spike.log to see what happened in more detail.
712 if __name__
== '__main__':