9 static inline int atomic_xchg(atomic_t
*v
, int n
)
13 __asm__
__volatile__ (
14 "amoswap.w.aqrl %0, %2, %1"
15 : "=r" (c
), "+A" (v
->counter
)
20 static inline void mb(void)
22 __asm__
__volatile__ ("fence");
25 void get_lock(atomic_t
*lock
)
27 while (atomic_xchg(lock
, 1) == 1)
32 void put_lock(atomic_t
*lock
)
38 static atomic_t buf_lock
= { .counter
= 0 };
40 static int buf_initialized
;
41 static unsigned hart_count
[NHARTS
];
42 static unsigned interrupt_count
[NHARTS
];
44 static unsigned delta
= 0x100;
45 void *increment_count(unsigned hartid
, unsigned mcause
, void *mepc
, void *sp
)
47 interrupt_count
[hartid
]++;
48 MTIMECMP
[hartid
] = MTIME
+ delta
;
54 uint32_t hartid
= csr_read(mhartid
);
55 hart_count
[hartid
] = 0;
56 interrupt_count
[hartid
] = 0;
58 set_trap_handler(increment_count
);
59 // Despite being memory-mapped, there appears to be one mtimecmp
60 // register per hart. The spec does not address this.
61 MTIMECMP
[hartid
] = MTIME
+ delta
;
62 enable_timer_interrupts();
67 if (!buf_initialized
) {
68 for (unsigned i
= 0; i
< sizeof(buf
); i
++) {
69 buf
[i
] = 'A' + (i
% 26);
75 int offset
= (first
& ~0x20) - 'A';
76 for (unsigned i
= 0; i
< sizeof(buf
); i
++) {
77 while (buf
[i
] != (first
- offset
+ ((offset
+ i
) % 26)))
81 buf
[i
] = 'A' + ((i
+ hartid
+ hart_count
[hartid
]) % 26);
83 buf
[i
] = 'a' + ((i
+ hartid
+ hart_count
[hartid
]) % 26);