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6da3ac509c5b53c7d75034983404b19159d6a945
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
Freedom
/
U500.py
1
import
targets
2
3
class
U500Hart
(
targets
.
Hart
):
4
xlen
=
64
5
ram
=
0x80000000
6
ram_size
=
16
*
1024
7
instruction_hardware_breakpoint_count
=
2
8
link_script_path
=
"Freedom.lds"
9
10
class
U500
(
targets
.
Target
):
11
openocd_config_path
=
"Freedom.cfg"
12
harts
= [
U500Hart
()]