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Mask medeleg correctly
[riscv-isa-sim.git]
/
debug_rom
/
link.ld
1
OUTPUT_ARCH( "riscv" )
2
ENTRY( entry )
3
SECTIONS
4
{
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.whereto 0x300 :
6
{
7
*(.whereto)
8
}
9
. = 0x800;
10
.text :
11
{
12
*(.text)
13
}
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_end = .;
15
}