decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 flush_in: in std_ulogic;
  20
  21                 d_in  : in Decode1ToDecode2Type;
  22
  23                 e_out : out Decode2ToExecute1Type;
  24                 m_out : out Decode2ToMultiplyType;
  25                 l_out : out Decode2ToLoadstore1Type;
  26
  27                 r_in  : in RegisterFileToDecode2Type;
  28                 r_out : out Decode2ToRegisterFileType;
  29
  30                 c_in  : in CrFileToDecode2Type;
  31                 c_out : out Decode2ToCrFileType
  32         );
  33 end entity decode2;
  34
  35 architecture behaviour of decode2 is
  36         type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
  37
  38         type reg_internal_type is record
  39                 state : state_type;
  40                 outstanding : integer;
  41         end record;
  42
  43         type reg_type is record
  44                 e : Decode2ToExecute1Type;
  45                 m : Decode2ToMultiplyType;
  46                 l : Decode2ToLoadstore1Type;
  47         end record;
  48
  49         signal r_int, rin_int : reg_internal_type;
  50         signal r, rin : reg_type;
  51
  52         type decode_input_reg_t is record
  53                 reg_valid : std_ulogic;
  54                 reg       : std_ulogic_vector(4 downto 0);
  55                 data      : std_ulogic_vector(63 downto 0);
  56         end record;
  57
  58         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  59                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  60         begin
  61                 case t is
  62                 when RA =>
  63                         return ('1', insn_ra(insn_in), reg_data);
  64                 when RA_OR_ZERO =>
  65                         return ('1', insn_ra(insn_in), ra_or_zero(reg_data, insn_ra(insn_in)));
  66                 when RS =>
  67                         return ('1', insn_rs(insn_in), reg_data);
  68                 when NONE =>
  69                         return ('0', (others => '0'), (others => '0'));
  70                 end case;
  71         end;
  72
  73         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  74                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  75         begin
  76                 case t is
  77                 when RB =>
  78                         return ('1', insn_rb(insn_in), reg_data);
  79                 when RS =>
  80                         return ('1', insn_rs(insn_in), reg_data);
  81                 when CONST_UI =>
  82                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  83                 when CONST_SI =>
  84                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  85                 when CONST_SI_HI =>
  86                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  87                 when CONST_UI_HI =>
  88                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  89                 when CONST_LI =>
  90                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  91                 when CONST_BD =>
  92                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  93                 when CONST_DS =>
  94                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  95                 when NONE =>
  96                         return ('0', (others => '0'), (others => '0'));
  97                 end case;
  98         end;
  99
 100         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 101                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 102         begin
 103                 case t is
 104                 when RS =>
 105                         return ('1', insn_rs(insn_in), reg_data);
 106                 when NONE =>
 107                         return ('0', (others => '0'), (others => '0'));
 108                 end case;
 109         end;
 110
 111         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 112         begin
 113                 case t is
 114                 when RT =>
 115                         return insn_rt(insn_in);
 116                 when RA =>
 117                         return insn_ra(insn_in);
 118                 when NONE =>
 119                         return "00000";
 120                 end case;
 121         end;
 122
 123         function decode_const_a (t : constant_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 124         begin
 125                 case t is
 126                 when SH =>
 127                         return "00" & insn_sh(insn_in);
 128                 when SH32 =>
 129                         return "000" & insn_sh32(insn_in);
 130                 when FXM =>
 131                         return insn_fxm(insn_in);
 132                 when BO =>
 133                         return "000" & insn_bo(insn_in);
 134                 when BF =>
 135                         return "00000" & insn_bf(insn_in);
 136                 when TOO =>
 137                         return "000" & insn_to(insn_in);
 138                 when BC =>
 139                         return "000" & insn_bc(insn_in);
 140                 when NONE =>
 141                         return "00000000";
 142                 end case;
 143         end;
 144
 145         function decode_const_b (t : constant_b_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 146         begin
 147                 case t is
 148                 when MB =>
 149                         return insn_mb(insn_in);
 150                 when ME =>
 151                         return insn_me(insn_in);
 152                 when MB32 =>
 153                         return "0" & insn_mb32(insn_in);
 154                 when BI =>
 155                         return "0" & insn_bi(insn_in);
 156                 when L =>
 157                         return "00000" & insn_l(insn_in);
 158                 when NONE =>
 159                         return "000000";
 160                 end case;
 161         end;
 162
 163         function decode_const_c (t : constant_c_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 164         begin
 165                 case t is
 166                 when ME32 =>
 167                         return insn_me32(insn_in);
 168                 when BH =>
 169                         return "000" & insn_bh(insn_in);
 170                 when NONE =>
 171                         return "00000";
 172                 end case;
 173         end;
 174
 175         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 176         begin
 177                 case t is
 178                 when RC =>
 179                         return insn_rc(insn_in);
 180                 when ONE =>
 181                         return '1';
 182                 when NONE =>
 183                         return '0';
 184                 end case;
 185         end;
 186 begin
 187
 188         decode2_0: process(clk)
 189         begin
 190                 if rising_edge(clk) then
 191                         assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
 192
 193                         if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' then
 194                                 report "execute " & to_hstring(rin.e.nia);
 195                         end if;
 196                         r <= rin;
 197                         r_int <= rin_int;
 198                 end if;
 199         end process;
 200
 201         r_out.read1_reg <= insn_ra(d_in.insn) when (d_in.decode.input_reg_a = RA) else
 202                            insn_ra(d_in.insn) when d_in.decode.input_reg_a = RA_OR_ZERO else
 203                            insn_rs(d_in.insn) when d_in.decode.input_reg_a = RS else
 204                            (others => '0');
 205
 206         r_out.read2_reg <= insn_rb(d_in.insn) when d_in.decode.input_reg_b = RB else
 207                            insn_rs(d_in.insn) when d_in.decode.input_reg_b = RS else
 208                            (others => '0');
 209
 210         r_out.read3_reg <= insn_rs(d_in.insn) when d_in.decode.input_reg_c = RS else
 211                            (others => '0');
 212
 213         c_out.read <= d_in.decode.input_cr;
 214
 215         decode2_1: process(all)
 216                 variable v : reg_type;
 217                 variable v_int : reg_internal_type;
 218                 variable mul_a : std_ulogic_vector(63 downto 0);
 219                 variable mul_b : std_ulogic_vector(63 downto 0);
 220                 variable decoded_reg_a : decode_input_reg_t;
 221                 variable decoded_reg_b : decode_input_reg_t;
 222                 variable decoded_reg_c : decode_input_reg_t;
 223                 variable is_valid : std_ulogic;
 224         begin
 225                 v := r;
 226                 v_int := r_int;
 227
 228                 v.e := Decode2ToExecute1Init;
 229                 v.l := Decode2ToLoadStore1Init;
 230                 v.m := Decode2ToMultiplyInit;
 231
 232                 mul_a := (others => '0');
 233                 mul_b := (others => '0');
 234
 235                 --v.e.input_cr := d_in.decode.input_cr;
 236                 --v.m.input_cr := d_in.decode.input_cr;
 237                 --v.e.output_cr := d_in.decode.output_cr;
 238
 239                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 240                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 241                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 242
 243                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 244                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 245                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 246
 247                 -- execute unit
 248                 v.e.nia := d_in.nia;
 249                 v.e.insn_type := d_in.decode.insn_type;
 250                 v.e.read_reg1 := decoded_reg_a.reg;
 251                 v.e.read_data1 := decoded_reg_a.data;
 252                 v.e.read_reg2 := decoded_reg_b.reg;
 253                 v.e.read_data2 := decoded_reg_b.data;
 254                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 255                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 256                 v.e.cr := c_in.read_cr_data;
 257                 v.e.input_carry := d_in.decode.input_carry;
 258                 v.e.output_carry := d_in.decode.output_carry;
 259                 if d_in.decode.lr = '1' then
 260                         v.e.lr := insn_lk(d_in.insn);
 261                 end if;
 262                 v.e.const1 := decode_const_a(d_in.decode.const_a, d_in.insn);
 263                 v.e.const2 := decode_const_b(d_in.decode.const_b, d_in.insn);
 264                 v.e.const3 := decode_const_c(d_in.decode.const_c, d_in.insn);
 265
 266                 -- multiply unit
 267                 v.m.insn_type := d_in.decode.insn_type;
 268                 mul_a := decoded_reg_a.data;
 269                 mul_b := decoded_reg_b.data;
 270                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 271                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 272
 273                 if d_in.decode.mul_32bit = '1' then
 274                         if d_in.decode.mul_signed = '1' then
 275                                 v.m.data1 := (others => mul_a(31));
 276                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 277                                 v.m.data2 := (others => mul_b(31));
 278                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 279                         else
 280                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 281                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 282                         end if;
 283                 else
 284                         if d_in.decode.mul_signed = '1' then
 285                                 v.m.data1 := mul_a(63) & mul_a;
 286                                 v.m.data2 := mul_b(63) & mul_b;
 287                         else
 288                                 v.m.data1 := '0' & mul_a;
 289                                 v.m.data2 := '0' & mul_b;
 290                         end if;
 291                 end if;
 292
 293                 -- load/store unit
 294                 v.l.update_reg := decoded_reg_a.reg;
 295                 v.l.addr1 := decoded_reg_a.data;
 296                 v.l.addr2 := decoded_reg_b.data;
 297                 v.l.data := decoded_reg_c.data;
 298                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 299
 300                 if d_in.decode.insn_type = OP_LOAD then
 301                         v.l.load := '1';
 302                 else
 303                         v.l.load := '0';
 304                 end if;
 305
 306                 case d_in.decode.length is
 307                 when is1B =>
 308                         v.l.length := "0001";
 309                 when is2B =>
 310                         v.l.length := "0010";
 311                 when is4B =>
 312                         v.l.length := "0100";
 313                 when is8B =>
 314                         v.l.length := "1000";
 315                 when NONE =>
 316                         v.l.length := "0000";
 317                 end case;
 318
 319                 v.l.byte_reverse := d_in.decode.byte_reverse;
 320                 v.l.sign_extend := d_in.decode.sign_extend;
 321                 v.l.update := d_in.decode.update;
 322
 323                 -- single issue
 324
 325                 if complete_in = '1' then
 326                         v_int.outstanding := v_int.outstanding - 1;
 327                 end if;
 328
 329                 -- state machine to handle instructions that must be single
 330                 -- through the pipeline.
 331                 stall_out <= '0';
 332                 is_valid := d_in.valid;
 333                 case v_int.state is
 334                 when IDLE =>
 335                         if (flush_in = '0') and (d_in.valid = '1') and (d_in.decode.sgl_pipe = '1') then
 336                                 if v_int.outstanding /= 0 then
 337                                         v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
 338                                         stall_out <= '1';
 339                                         is_valid := '0';
 340                                 else
 341                                         -- send insn out and wait on it to complete
 342                                         v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 343                                 end if;
 344                         end if;
 345
 346                 when WAIT_FOR_PREV_TO_COMPLETE =>
 347                         if v_int.outstanding = 0 then
 348                                 -- send insn out and wait on it to complete
 349                                 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 350                         else
 351                                 stall_out <= '1';
 352                                 is_valid := '0';
 353                         end if;
 354
 355                 when WAIT_FOR_CURR_TO_COMPLETE =>
 356                         if v_int.outstanding = 0 then
 357                                 v_int.state := IDLE;
 358                         else
 359                                 stall_out <= '1';
 360                                 is_valid := '0';
 361                         end if;
 362                 end case;
 363
 364                 v.e.valid := '0';
 365                 v.m.valid := '0';
 366                 v.l.valid := '0';
 367                 case d_in.decode.unit is
 368                 when ALU =>
 369                         v.e.valid := is_valid;
 370                 when LDST =>
 371                         v.l.valid := is_valid;
 372                 when MUL =>
 373                         v.m.valid := is_valid;
 374                 when NONE =>
 375                         v.e.valid := is_valid;
 376                         v.e.insn_type := OP_ILLEGAL;
 377                 end case;
 378
 379                 if flush_in = '1' then
 380                         v.e.valid := '0';
 381                         v.m.valid := '0';
 382                         v.l.valid := '0';
 383                 end if;
 384
 385                 -- track outstanding instructions
 386                 if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' then
 387                         v_int.outstanding := v_int.outstanding + 1;
 388                 end if;
 389
 390                 if rst = '1' then
 391                         v_int.state := IDLE;
 392                         v_int.outstanding := 0;
 393                         v.e := Decode2ToExecute1Init;
 394                         v.l := Decode2ToLoadStore1Init;
 395                         v.m := Decode2ToMultiplyInit;
 396                 end if;
 397
 398                 -- Update registers
 399                 rin <= v;
 400                 rin_int <= v_int;
 401
 402                 -- Update outputs
 403                 e_out <= r.e;
 404                 l_out <= r.l;
 405                 m_out <= r.m;
 406         end process;
 407 end architecture behaviour;