2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.insn_helpers.all;
13 EX1_BYPASS : boolean := true
19 complete_in : in std_ulogic;
20 stall_in : in std_ulogic;
21 stall_out : out std_ulogic;
23 stopped_out : out std_ulogic;
25 flush_in: in std_ulogic;
27 d_in : in Decode1ToDecode2Type;
29 e_out : out Decode2ToExecute1Type;
31 r_in : in RegisterFileToDecode2Type;
32 r_out : out Decode2ToRegisterFileType;
34 c_in : in CrFileToDecode2Type;
35 c_out : out Decode2ToCrFileType
39 architecture behaviour of decode2 is
40 type reg_type is record
41 e : Decode2ToExecute1Type;
44 signal r, rin : reg_type;
46 type decode_input_reg_t is record
47 reg_valid : std_ulogic;
49 data : std_ulogic_vector(63 downto 0);
52 type decode_output_reg_t is record
53 reg_valid : std_ulogic;
57 function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
58 reg_data : std_ulogic_vector(63 downto 0);
60 instr_addr : std_ulogic_vector(63 downto 0))
61 return decode_input_reg_t is
63 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
64 assert is_fast_spr(ispr) = '0' report "Decode A says GPR but ISPR says SPR:" &
65 to_hstring(ispr) severity failure;
66 return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
68 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
69 -- If it's all 0, we don't treat it as a dependency as slow SPRs
70 -- operations are single issue.
72 assert is_fast_spr(ispr) = '1' or ispr = "000000"
73 report "Decode A says SPR but ISPR is invalid:" &
74 to_hstring(ispr) severity failure;
75 return (is_fast_spr(ispr), ispr, reg_data);
77 return ('0', (others => '0'), instr_addr);
79 return ('0', (others => '0'), (others => '0'));
83 function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
84 reg_data : std_ulogic_vector(63 downto 0);
85 ispr : gspr_index_t) return decode_input_reg_t is
86 variable ret : decode_input_reg_t;
90 assert is_fast_spr(ispr) = '0' report "Decode B says GPR but ISPR says SPR:" &
91 to_hstring(ispr) severity failure;
92 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
94 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
96 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
98 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
100 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
102 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
104 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
106 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
108 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
110 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
112 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
114 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
116 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
117 -- If it's all 0, we don't treat it as a dependency as slow SPRs
118 -- operations are single issue.
119 assert is_fast_spr(ispr) = '1' or ispr = "000000"
120 report "Decode B says SPR but ISPR is invalid:" &
121 to_hstring(ispr) severity failure;
122 ret := (is_fast_spr(ispr), ispr, reg_data);
124 ret := ('0', (others => '0'), (others => '0'));
130 function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
131 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
135 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
137 return ('0', (others => '0'), (others => '0'));
141 function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
142 ispr : gspr_index_t) return decode_output_reg_t is
146 return ('1', gpr_to_gspr(insn_rt(insn_in)));
148 return ('1', gpr_to_gspr(insn_ra(insn_in)));
150 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
151 -- If it's all 0, we don't treat it as a dependency as slow SPRs
152 -- operations are single issue.
153 assert is_fast_spr(ispr) = '1' or ispr = "000000"
154 report "Decode B says SPR but ISPR is invalid:" &
155 to_hstring(ispr) severity failure;
156 return (is_fast_spr(ispr), ispr);
158 return ('0', "000000");
162 function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
166 return insn_rc(insn_in);
174 -- For now, use "rc" in the decode table to decide whether oe exists.
175 -- This is not entirely correct architecturally: For mulhd and
176 -- mulhdu, the OE field is reserved. It remains to be seen what an
177 -- actual POWER9 does if we set it on those instructions, for now we
178 -- test that further down when assigning to the multiplier oe input.
180 function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
184 return insn_oe(insn_in);
190 -- issue control signals
191 signal control_valid_in : std_ulogic;
192 signal control_valid_out : std_ulogic;
193 signal control_sgl_pipe : std_logic;
195 signal gpr_write_valid : std_ulogic;
196 signal gpr_write : gspr_index_t;
197 signal gpr_bypassable : std_ulogic;
199 signal gpr_a_read_valid : std_ulogic;
200 signal gpr_a_read :gspr_index_t;
201 signal gpr_a_bypass : std_ulogic;
203 signal gpr_b_read_valid : std_ulogic;
204 signal gpr_b_read : gspr_index_t;
205 signal gpr_b_bypass : std_ulogic;
207 signal gpr_c_read_valid : std_ulogic;
208 signal gpr_c_read : gpr_index_t;
209 signal gpr_c_bypass : std_ulogic;
211 signal cr_write_valid : std_ulogic;
213 control_0: entity work.control
221 complete_in => complete_in,
222 valid_in => control_valid_in,
223 stall_in => stall_in,
224 flush_in => flush_in,
225 sgl_pipe_in => control_sgl_pipe,
226 stop_mark_in => d_in.stop_mark,
228 gpr_write_valid_in => gpr_write_valid,
229 gpr_write_in => gpr_write,
230 gpr_bypassable => gpr_bypassable,
232 gpr_a_read_valid_in => gpr_a_read_valid,
233 gpr_a_read_in => gpr_a_read,
235 gpr_b_read_valid_in => gpr_b_read_valid,
236 gpr_b_read_in => gpr_b_read,
238 gpr_c_read_valid_in => gpr_c_read_valid,
239 gpr_c_read_in => gpr_c_read,
241 cr_read_in => d_in.decode.input_cr,
242 cr_write_in => cr_write_valid,
244 valid_out => control_valid_out,
245 stall_out => stall_out,
246 stopped_out => stopped_out,
248 gpr_bypass_a => gpr_a_bypass,
249 gpr_bypass_b => gpr_b_bypass,
250 gpr_bypass_c => gpr_c_bypass
253 decode2_0: process(clk)
255 if rising_edge(clk) then
256 if rin.e.valid = '1' then
257 report "execute " & to_hstring(rin.e.nia);
263 r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn), d_in.ispr1);
264 r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn), d_in.ispr2);
265 r_out.read3_reg <= insn_rs(d_in.insn);
267 c_out.read <= d_in.decode.input_cr;
269 decode2_1: process(all)
270 variable v : reg_type;
271 variable mul_a : std_ulogic_vector(63 downto 0);
272 variable mul_b : std_ulogic_vector(63 downto 0);
273 variable decoded_reg_a : decode_input_reg_t;
274 variable decoded_reg_b : decode_input_reg_t;
275 variable decoded_reg_c : decode_input_reg_t;
276 variable decoded_reg_o : decode_output_reg_t;
277 variable length : std_ulogic_vector(3 downto 0);
281 v.e := Decode2ToExecute1Init;
283 mul_a := (others => '0');
284 mul_b := (others => '0');
286 --v.e.input_cr := d_in.decode.input_cr;
287 --v.e.output_cr := d_in.decode.output_cr;
289 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
291 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
292 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
293 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispr1);
295 r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
296 r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
297 r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
299 case d_in.decode.length is
314 v.e.unit := d_in.decode.unit;
315 v.e.insn_type := d_in.decode.insn_type;
316 v.e.read_reg1 := decoded_reg_a.reg;
317 v.e.read_data1 := decoded_reg_a.data;
318 v.e.bypass_data1 := gpr_a_bypass;
319 v.e.read_reg2 := decoded_reg_b.reg;
320 v.e.read_data2 := decoded_reg_b.data;
321 v.e.bypass_data2 := gpr_b_bypass;
322 v.e.read_data3 := decoded_reg_c.data;
323 v.e.bypass_data3 := gpr_c_bypass;
324 v.e.write_reg := decoded_reg_o.reg;
325 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
326 if not (d_in.decode.insn_type = OP_MUL_H32 or d_in.decode.insn_type = OP_MUL_H64) then
327 v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
329 v.e.cr := c_in.read_cr_data;
330 v.e.xerc := c_in.read_xerc_data;
331 v.e.invert_a := d_in.decode.invert_a;
332 v.e.invert_out := d_in.decode.invert_out;
333 v.e.input_carry := d_in.decode.input_carry;
334 v.e.output_carry := d_in.decode.output_carry;
335 v.e.is_32bit := d_in.decode.is_32bit;
336 v.e.is_signed := d_in.decode.is_signed;
337 if d_in.decode.lr = '1' then
338 v.e.lr := insn_lk(d_in.insn);
340 v.e.insn := d_in.insn;
341 v.e.data_len := length;
342 v.e.byte_reverse := d_in.decode.byte_reverse;
343 v.e.sign_extend := d_in.decode.sign_extend;
344 v.e.update := d_in.decode.update;
345 v.e.reserve := d_in.decode.reserve;
348 control_valid_in <= d_in.valid;
349 control_sgl_pipe <= d_in.decode.sgl_pipe;
351 gpr_write_valid <= decoded_reg_o.reg_valid;
352 gpr_write <= decoded_reg_o.reg;
353 gpr_bypassable <= '0';
354 if EX1_BYPASS and d_in.decode.unit = ALU then
355 gpr_bypassable <= '1';
358 gpr_a_read_valid <= decoded_reg_a.reg_valid;
359 gpr_a_read <= decoded_reg_a.reg;
361 gpr_b_read_valid <= decoded_reg_b.reg_valid;
362 gpr_b_read <= decoded_reg_b.reg;
364 gpr_c_read_valid <= decoded_reg_c.reg_valid;
365 gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
367 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
369 v.e.valid := control_valid_out;
370 if d_in.decode.unit = NONE then
371 v.e.insn_type := OP_ILLEGAL;
375 v.e := Decode2ToExecute1Init;
384 end architecture behaviour;