2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
9 use work.insn_helpers.all;
13 EX1_BYPASS : boolean := true;
14 HAS_FPU : boolean := true;
15 -- Non-zero to enable log data collection
16 LOG_LENGTH : natural := 0
22 complete_in : in instr_tag_t;
23 busy_in : in std_ulogic;
24 stall_out : out std_ulogic;
26 stopped_out : out std_ulogic;
28 flush_in: in std_ulogic;
30 d_in : in Decode1ToDecode2Type;
32 e_out : out Decode2ToExecute1Type;
34 r_in : in RegisterFileToDecode2Type;
35 r_out : out Decode2ToRegisterFileType;
37 c_in : in CrFileToDecode2Type;
38 c_out : out Decode2ToCrFileType;
40 execute_bypass : in bypass_data_t;
41 execute_cr_bypass : in cr_bypass_data_t;
43 log_out : out std_ulogic_vector(9 downto 0)
47 architecture behaviour of decode2 is
48 type reg_type is record
49 e : Decode2ToExecute1Type;
53 signal r, rin : reg_type;
55 signal deferred : std_ulogic;
57 type decode_input_reg_t is record
58 reg_valid : std_ulogic;
60 data : std_ulogic_vector(63 downto 0);
63 type decode_output_reg_t is record
64 reg_valid : std_ulogic;
68 function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
69 reg_data : std_ulogic_vector(63 downto 0);
71 instr_addr : std_ulogic_vector(63 downto 0))
72 return decode_input_reg_t is
74 if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
75 return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
77 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
78 -- If it's all 0, we don't treat it as a dependency as slow SPRs
79 -- operations are single issue.
81 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
82 report "Decode A says SPR but ISPR is invalid:" &
83 to_hstring(ispr) severity failure;
84 return (is_fast_spr(ispr), ispr, reg_data);
86 return ('0', (others => '0'), instr_addr);
87 elsif HAS_FPU and t = FRA then
88 return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
90 return ('0', (others => '0'), (others => '0'));
94 function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
95 reg_data : std_ulogic_vector(63 downto 0);
96 ispr : gspr_index_t) return decode_input_reg_t is
97 variable ret : decode_input_reg_t;
101 ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
104 ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
106 ret := ('0', (others => '0'), (others => '0'));
109 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
111 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
113 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
115 ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
117 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
119 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
121 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
123 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
125 ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
127 ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
129 ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
131 ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
133 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
134 -- If it's all 0, we don't treat it as a dependency as slow SPRs
135 -- operations are single issue.
136 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
137 report "Decode B says SPR but ISPR is invalid:" &
138 to_hstring(ispr) severity failure;
139 ret := (is_fast_spr(ispr), ispr, reg_data);
141 ret := ('0', (others => '0'), (others => '0'));
147 function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
148 reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
152 return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
154 return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
157 return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
159 return ('0', (others => '0'), (others => '0'));
163 return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
165 return ('0', (others => '0'), (others => '0'));
168 return ('0', (others => '0'), (others => '0'));
172 function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
173 ispr : gspr_index_t) return decode_output_reg_t is
177 return ('1', gpr_to_gspr(insn_rt(insn_in)));
179 return ('1', gpr_to_gspr(insn_ra(insn_in)));
182 return ('1', fpr_to_gspr(insn_frt(insn_in)));
184 return ('0', "0000000");
187 -- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
188 -- If it's all 0, we don't treat it as a dependency as slow SPRs
189 -- operations are single issue.
190 assert is_fast_spr(ispr) = '1' or ispr = "0000000"
191 report "Decode B says SPR but ISPR is invalid:" &
192 to_hstring(ispr) severity failure;
193 return (is_fast_spr(ispr), ispr);
195 return ('0', "0000000");
199 function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
203 return insn_rc(insn_in);
211 -- control signals that are derived from insn_type
212 type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
214 constant result_select : mux_select_array_t := (
215 OP_AND => "001", -- logical_result
225 OP_RLC => "010", -- rotator_result
230 OP_EXTSWSLI => "010",
231 OP_MUL_L64 => "011", -- muldiv_result
237 OP_CNTZ => "100", -- countzero_result
238 OP_MFSPR => "101", -- spr_result
239 OP_B => "110", -- next_nia
242 OP_ADDG6S => "111", -- misc_result
248 others => "000" -- default to adder_result
251 constant subresult_select : mux_select_array_t := (
252 OP_MUL_L64 => "000", -- muldiv_result
258 OP_ADDG6S => "001", -- misc_result
264 OP_CMP => "000", -- cr_result
273 -- issue control signals
274 signal control_valid_in : std_ulogic;
275 signal control_valid_out : std_ulogic;
276 signal control_stall_out : std_ulogic;
277 signal control_sgl_pipe : std_logic;
279 signal gpr_write_valid : std_ulogic;
280 signal gpr_write : gspr_index_t;
282 signal gpr_a_read_valid : std_ulogic;
283 signal gpr_a_read : gspr_index_t;
284 signal gpr_a_bypass : std_ulogic;
286 signal gpr_b_read_valid : std_ulogic;
287 signal gpr_b_read : gspr_index_t;
288 signal gpr_b_bypass : std_ulogic;
290 signal gpr_c_read_valid : std_ulogic;
291 signal gpr_c_read : gspr_index_t;
292 signal gpr_c_bypass : std_ulogic;
294 signal cr_read_valid : std_ulogic;
295 signal cr_write_valid : std_ulogic;
296 signal cr_bypass : std_ulogic;
298 signal instr_tag : instr_tag_t;
301 control_0: entity work.control
303 EX1_BYPASS => EX1_BYPASS
309 complete_in => complete_in,
310 valid_in => control_valid_in,
311 repeated => r.repeat,
313 deferred => deferred,
314 flush_in => flush_in,
315 sgl_pipe_in => control_sgl_pipe,
316 stop_mark_in => d_in.stop_mark,
318 gpr_write_valid_in => gpr_write_valid,
319 gpr_write_in => gpr_write,
321 gpr_a_read_valid_in => gpr_a_read_valid,
322 gpr_a_read_in => gpr_a_read,
324 gpr_b_read_valid_in => gpr_b_read_valid,
325 gpr_b_read_in => gpr_b_read,
327 gpr_c_read_valid_in => gpr_c_read_valid,
328 gpr_c_read_in => gpr_c_read,
330 execute_next_tag => execute_bypass.tag,
331 execute_next_cr_tag => execute_cr_bypass.tag,
333 cr_read_in => cr_read_valid,
334 cr_write_in => cr_write_valid,
335 cr_bypass => cr_bypass,
337 valid_out => control_valid_out,
338 stall_out => control_stall_out,
339 stopped_out => stopped_out,
341 gpr_bypass_a => gpr_a_bypass,
342 gpr_bypass_b => gpr_b_bypass,
343 gpr_bypass_c => gpr_c_bypass,
345 instr_tag_out => instr_tag
348 deferred <= r.e.valid and busy_in;
350 decode2_0: process(clk)
352 if rising_edge(clk) then
353 if rst = '1' or flush_in = '1' or deferred = '0' then
354 if rin.e.valid = '1' then
355 report "execute " & to_hstring(rin.e.nia);
362 c_out.read <= d_in.decode.input_cr;
364 decode2_1: process(all)
365 variable v : reg_type;
366 variable mul_a : std_ulogic_vector(63 downto 0);
367 variable mul_b : std_ulogic_vector(63 downto 0);
368 variable decoded_reg_a : decode_input_reg_t;
369 variable decoded_reg_b : decode_input_reg_t;
370 variable decoded_reg_c : decode_input_reg_t;
371 variable decoded_reg_o : decode_output_reg_t;
372 variable length : std_ulogic_vector(3 downto 0);
373 variable op : insn_type_t;
377 v.e := Decode2ToExecute1Init;
379 mul_a := (others => '0');
380 mul_b := (others => '0');
382 --v.e.input_cr := d_in.decode.input_cr;
383 v.e.output_cr := d_in.decode.output_cr;
385 -- Work out whether XER common bits are set
386 v.e.output_xer := d_in.decode.output_carry;
387 case d_in.decode.insn_type is
388 when OP_ADD | OP_MUL_L64 | OP_DIV | OP_DIVE =>
389 -- OE field is valid in OP_ADD/OP_MUL_L64 with major opcode 31 only
390 if d_in.insn(31 downto 26) = "011111" and insn_oe(d_in.insn) = '1' then
392 v.e.output_xer := '1';
395 if decode_spr_num(d_in.insn) = SPR_XER then
396 v.e.output_xer := '1';
401 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
403 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
404 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
405 decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispro);
407 if d_in.decode.lr = '1' then
408 v.e.lr := insn_lk(d_in.insn);
409 -- b and bc have even major opcodes; bcreg is considered absolute
410 v.e.br_abs := insn_aa(d_in.insn) or d_in.insn(26);
412 op := d_in.decode.insn_type;
414 if d_in.decode.repeat /= NONE then
416 v.e.second := r.repeat;
417 case d_in.decode.repeat is
419 -- do RS|1,RS for LE; RS,RS|1 for BE
420 if r.repeat = d_in.big_endian then
421 decoded_reg_c.reg(0) := '1';
424 -- do RT|1,RT for LE; RT,RT|1 for BE
425 if r.repeat = d_in.big_endian then
426 decoded_reg_o.reg(0) := '1';
429 -- update-form loads, 2nd instruction writes RA
430 if r.repeat = '1' then
431 decoded_reg_o.reg := decoded_reg_a.reg;
435 elsif v.e.lr = '1' and decoded_reg_a.reg_valid = '1' then
436 -- bcl/bclrl/bctarl that needs to write both CTR and LR has to be doubled
438 v.e.second := r.repeat;
439 -- first one does CTR, second does LR
440 decoded_reg_o.reg(0) := not r.repeat;
443 r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
444 r_out.read1_reg <= decoded_reg_a.reg;
445 r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
446 r_out.read2_reg <= decoded_reg_b.reg;
447 r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
448 r_out.read3_reg <= decoded_reg_c.reg;
450 case d_in.decode.length is
465 v.e.unit := d_in.decode.unit;
466 v.e.fac := d_in.decode.facility;
467 v.e.instr_tag := instr_tag;
468 v.e.read_reg1 := decoded_reg_a.reg;
469 v.e.read_reg2 := decoded_reg_b.reg;
470 v.e.write_reg := decoded_reg_o.reg;
471 v.e.write_reg_enable := decoded_reg_o.reg_valid;
472 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
473 v.e.xerc := c_in.read_xerc_data;
474 v.e.invert_a := d_in.decode.invert_a;
477 v.e.invert_out := d_in.decode.invert_out;
478 v.e.input_carry := d_in.decode.input_carry;
479 v.e.output_carry := d_in.decode.output_carry;
480 v.e.is_32bit := d_in.decode.is_32bit;
481 v.e.is_signed := d_in.decode.is_signed;
482 v.e.insn := d_in.insn;
483 v.e.data_len := length;
484 v.e.byte_reverse := d_in.decode.byte_reverse;
485 v.e.sign_extend := d_in.decode.sign_extend;
486 v.e.update := d_in.decode.update;
487 v.e.reserve := d_in.decode.reserve;
488 v.e.br_pred := d_in.br_pred;
489 v.e.result_sel := result_select(op);
490 v.e.sub_select := subresult_select(op);
491 if op = OP_BC or op = OP_BCREG then
492 if d_in.insn(23) = '0' and r.repeat = '0' and
493 not (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
494 -- decrement CTR if BO(2) = 0 and not bcctr
496 v.e.result_sel := "000"; -- select adder output
500 -- See if any of the operands can get their value via the bypass path.
503 v.e.read_data1 := execute_bypass.data;
505 v.e.read_data1 := decoded_reg_a.data;
509 v.e.read_data2 := execute_bypass.data;
511 v.e.read_data2 := decoded_reg_b.data;
515 v.e.read_data3 := execute_bypass.data;
517 v.e.read_data3 := decoded_reg_c.data;
520 v.e.cr := c_in.read_cr_data;
521 if cr_bypass = '1' then
522 v.e.cr := execute_cr_bypass.data;
526 control_valid_in <= d_in.valid;
527 control_sgl_pipe <= d_in.decode.sgl_pipe;
529 gpr_write_valid <= v.e.write_reg_enable;
530 gpr_write <= decoded_reg_o.reg;
532 gpr_a_read_valid <= decoded_reg_a.reg_valid;
533 gpr_a_read <= decoded_reg_a.reg;
535 gpr_b_read_valid <= decoded_reg_b.reg_valid;
536 gpr_b_read <= decoded_reg_b.reg;
538 gpr_c_read_valid <= decoded_reg_c.reg_valid;
539 gpr_c_read <= decoded_reg_c.reg;
541 cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
542 -- Since ops that write CR only write some of the fields,
543 -- any op that writes CR effectively also reads it.
544 cr_read_valid <= cr_write_valid or d_in.decode.input_cr;
546 v.e.valid := control_valid_out;
547 if control_valid_out = '1' then
548 v.repeat := v.e.repeat and not r.repeat;
551 stall_out <= control_stall_out or v.repeat;
553 if rst = '1' or flush_in = '1' then
554 v.e := Decode2ToExecute1Init;
565 d2_log: if LOG_LENGTH > 0 generate
566 signal log_data : std_ulogic_vector(9 downto 0);
568 dec2_log : process(clk)
570 if rising_edge(clk) then
571 log_data <= r.e.nia(5 downto 2) &
583 end architecture behaviour;