decode2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.insn_helpers.all;
  10
  11 entity decode2 is
  12         port (
  13                 clk   : in std_ulogic;
  14                 rst   : in std_ulogic;
  15
  16                 complete_in : in std_ulogic;
  17                 stall_out : out std_ulogic;
  18
  19                 flush_in: in std_ulogic;
  20
  21                 d_in  : in Decode1ToDecode2Type;
  22
  23                 e_out : out Decode2ToExecute1Type;
  24                 m_out : out Decode2ToMultiplyType;
  25                 l_out : out Decode2ToLoadstore1Type;
  26
  27                 r_in  : in RegisterFileToDecode2Type;
  28                 r_out : out Decode2ToRegisterFileType;
  29
  30                 c_in  : in CrFileToDecode2Type;
  31                 c_out : out Decode2ToCrFileType
  32         );
  33 end entity decode2;
  34
  35 architecture behaviour of decode2 is
  36         type state_type is (IDLE, WAIT_FOR_PREV_TO_COMPLETE, WAIT_FOR_CURR_TO_COMPLETE);
  37
  38         type reg_internal_type is record
  39                 state : state_type;
  40                 outstanding : integer;
  41         end record;
  42
  43         type reg_type is record
  44                 e : Decode2ToExecute1Type;
  45                 m : Decode2ToMultiplyType;
  46                 l : Decode2ToLoadstore1Type;
  47         end record;
  48
  49         signal r_int, rin_int : reg_internal_type;
  50         signal r, rin : reg_type;
  51
  52         type decode_input_reg_t is record
  53                 reg_valid : std_ulogic;
  54                 reg       : std_ulogic_vector(4 downto 0);
  55                 data      : std_ulogic_vector(63 downto 0);
  56         end record;
  57
  58         function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
  59                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  60         begin
  61                 case t is
  62                 when RA =>
  63                         return ('1', insn_ra(insn_in), reg_data);
  64                 when RA_OR_ZERO =>
  65                         return ('1', insn_ra(insn_in), ra_or_zero(reg_data, insn_ra(insn_in)));
  66                 when RS =>
  67                         return ('1', insn_rs(insn_in), reg_data);
  68                 when NONE =>
  69                         return ('0', (others => '0'), (others => '0'));
  70                 end case;
  71         end;
  72
  73         function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
  74                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
  75         begin
  76                 case t is
  77                 when RB =>
  78                         return ('1', insn_rb(insn_in), reg_data);
  79                 when RS =>
  80                         return ('1', insn_rs(insn_in), reg_data);
  81                 when CONST_UI =>
  82                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
  83                 when CONST_SI =>
  84                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
  85                 when CONST_SI_HI =>
  86                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
  87                 when CONST_UI_HI =>
  88                         return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
  89                 when CONST_LI =>
  90                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
  91                 when CONST_BD =>
  92                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
  93                 when CONST_DS =>
  94                         return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
  95                 when NONE =>
  96                         return ('0', (others => '0'), (others => '0'));
  97                 end case;
  98         end;
  99
 100         function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
 101                                      reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
 102         begin
 103                 case t is
 104                 when RS =>
 105                         return ('1', insn_rs(insn_in), reg_data);
 106                 when NONE =>
 107                         return ('0', (others => '0'), (others => '0'));
 108                 end case;
 109         end;
 110
 111         function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 112         begin
 113                 case t is
 114                 when RT =>
 115                         return insn_rt(insn_in);
 116                 when RA =>
 117                         return insn_ra(insn_in);
 118                 when NONE =>
 119                         return "00000";
 120                 end case;
 121         end;
 122
 123         function decode_const_a (t : constant_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 124         begin
 125                 case t is
 126                 when SH =>
 127                         return "00" & insn_sh(insn_in);
 128                 when SH32 =>
 129                         return "000" & insn_sh32(insn_in);
 130                 when FXM =>
 131                         return insn_fxm(insn_in);
 132                 when BO =>
 133                         return "000" & insn_bo(insn_in);
 134                 when BF =>
 135                         return "00000" & insn_bf(insn_in);
 136                 when TOO =>
 137                         return "000" & insn_to(insn_in);
 138                 when BC =>
 139                         return "000" & insn_bc(insn_in);
 140                 when NONE =>
 141                         return "00000000";
 142                 end case;
 143         end;
 144
 145         function decode_const_b (t : constant_b_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 146         begin
 147                 case t is
 148                 when MB =>
 149                         return insn_mb(insn_in);
 150                 when ME =>
 151                         return insn_me(insn_in);
 152                 when MB32 =>
 153                         return "0" & insn_mb32(insn_in);
 154                 when BI =>
 155                         return "0" & insn_bi(insn_in);
 156                 when L =>
 157                         return "00000" & insn_l(insn_in);
 158                 when NONE =>
 159                         return "000000";
 160                 end case;
 161         end;
 162
 163         function decode_const_c (t : constant_c_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
 164         begin
 165                 case t is
 166                 when ME32 =>
 167                         return insn_me32(insn_in);
 168                 when BH =>
 169                         return "000" & insn_bh(insn_in);
 170                 when NONE =>
 171                         return "00000";
 172                 end case;
 173         end;
 174
 175         function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
 176         begin
 177                 case t is
 178                 when RC =>
 179                         return insn_rc(insn_in);
 180                 when ONE =>
 181                         return '1';
 182                 when NONE =>
 183                         return '0';
 184                 end case;
 185         end;
 186 begin
 187
 188         decode2_0: process(clk)
 189         begin
 190                 if rising_edge(clk) then
 191                         if rin.e.valid = '1' then
 192                                 report "execute " & to_hstring(rin.e.nia);
 193                         end if;
 194                         if rin.l.valid = '1' then
 195                                 report "execute " & to_hstring(rin.e.nia);
 196                         end if;
 197                         if rin.m.valid = '1' then
 198                                 report "execute " & to_hstring(rin.e.nia);
 199                         end if;
 200                         r <= rin;
 201                         r_int <= rin_int;
 202                 end if;
 203         end process;
 204
 205         r_out.read1_reg <= insn_ra(d_in.insn) when (d_in.decode.input_reg_a = RA) else
 206                            insn_ra(d_in.insn) when d_in.decode.input_reg_a = RA_OR_ZERO else
 207                            insn_rs(d_in.insn) when d_in.decode.input_reg_a = RS else
 208                            (others => '0');
 209
 210         r_out.read2_reg <= insn_rb(d_in.insn) when d_in.decode.input_reg_b = RB else
 211                            insn_rs(d_in.insn) when d_in.decode.input_reg_b = RS else
 212                            (others => '0');
 213
 214         r_out.read3_reg <= insn_rs(d_in.insn) when d_in.decode.input_reg_c = RS else
 215                            (others => '0');
 216
 217         c_out.read <= d_in.decode.input_cr;
 218
 219         decode2_1: process(all)
 220                 variable v : reg_type;
 221                 variable v_int : reg_internal_type;
 222                 variable mul_a : std_ulogic_vector(63 downto 0);
 223                 variable mul_b : std_ulogic_vector(63 downto 0);
 224                 variable decoded_reg_a : decode_input_reg_t;
 225                 variable decoded_reg_b : decode_input_reg_t;
 226                 variable decoded_reg_c : decode_input_reg_t;
 227                 variable is_valid : std_ulogic;
 228         begin
 229                 v := r;
 230                 v_int := r_int;
 231
 232                 v.e := Decode2ToExecute1Init;
 233                 v.l := Decode2ToLoadStore1Init;
 234                 v.m := Decode2ToMultiplyInit;
 235
 236                 mul_a := (others => '0');
 237                 mul_b := (others => '0');
 238
 239                 --v.e.input_cr := d_in.decode.input_cr;
 240                 --v.m.input_cr := d_in.decode.input_cr;
 241                 --v.e.output_cr := d_in.decode.output_cr;
 242
 243                 decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
 244                 decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
 245                 decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
 246
 247                 r_out.read1_enable <= decoded_reg_a.reg_valid;
 248                 r_out.read2_enable <= decoded_reg_b.reg_valid;
 249                 r_out.read3_enable <= decoded_reg_c.reg_valid;
 250
 251                 -- execute unit
 252                 v.e.nia := d_in.nia;
 253                 v.e.insn_type := d_in.decode.insn_type;
 254                 v.e.read_reg1 := decoded_reg_a.reg;
 255                 v.e.read_data1 := decoded_reg_a.data;
 256                 v.e.read_reg2 := decoded_reg_b.reg;
 257                 v.e.read_data2 := decoded_reg_b.data;
 258                 v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 259                 v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
 260                 v.e.cr := c_in.read_cr_data;
 261                 v.e.input_carry := d_in.decode.input_carry;
 262                 v.e.output_carry := d_in.decode.output_carry;
 263                 if d_in.decode.lr then
 264                         v.e.lr := insn_lk(d_in.insn);
 265                 end if;
 266                 v.e.const1 := decode_const_a(d_in.decode.const_a, d_in.insn);
 267                 v.e.const2 := decode_const_b(d_in.decode.const_b, d_in.insn);
 268                 v.e.const3 := decode_const_c(d_in.decode.const_c, d_in.insn);
 269
 270                 -- multiply unit
 271                 v.m.nia := d_in.nia;
 272                 v.m.insn_type := d_in.decode.insn_type;
 273                 mul_a := decoded_reg_a.data;
 274                 mul_b := decoded_reg_b.data;
 275                 v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 276                 v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
 277
 278                 if d_in.decode.mul_32bit = '1' then
 279                         if d_in.decode.mul_signed = '1' then
 280                                 v.m.data1 := (others => mul_a(31));
 281                                 v.m.data1(31 downto 0) := mul_a(31 downto 0);
 282                                 v.m.data2 := (others => mul_b(31));
 283                                 v.m.data2(31 downto 0) := mul_b(31 downto 0);
 284                         else
 285                                 v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
 286                                 v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
 287                         end if;
 288                 else
 289                         if d_in.decode.mul_signed = '1' then
 290                                 v.m.data1 := mul_a(63) & mul_a;
 291                                 v.m.data2 := mul_b(63) & mul_b;
 292                         else
 293                                 v.m.data1 := '0' & mul_a;
 294                                 v.m.data2 := '0' & mul_b;
 295                         end if;
 296                 end if;
 297
 298                 -- load/store unit
 299                 v.l.nia := d_in.nia;
 300                 v.l.update_reg := decoded_reg_a.reg;
 301                 v.l.addr1 := decoded_reg_a.data;
 302                 v.l.addr2 := decoded_reg_b.data;
 303                 v.l.data := decoded_reg_c.data;
 304                 v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
 305
 306                 if d_in.decode.insn_type = OP_LOAD then
 307                         v.l.load := '1';
 308                 else
 309                         v.l.load := '0';
 310                 end if;
 311
 312                 case d_in.decode.length is
 313                 when is1B =>
 314                         v.l.length := "0001";
 315                 when is2B =>
 316                         v.l.length := "0010";
 317                 when is4B =>
 318                         v.l.length := "0100";
 319                 when is8B =>
 320                         v.l.length := "1000";
 321                 when NONE =>
 322                         v.l.length := "0000";
 323                 end case;
 324
 325                 v.l.byte_reverse := d_in.decode.byte_reverse;
 326                 v.l.sign_extend := d_in.decode.sign_extend;
 327                 v.l.update := d_in.decode.update;
 328
 329                 -- single issue
 330
 331                 if complete_in = '1' then
 332                         v_int.outstanding := v_int.outstanding - 1;
 333                 end if;
 334
 335                 -- state machine to handle instructions that must be single
 336                 -- through the pipeline.
 337                 stall_out <= '0';
 338                 is_valid := d_in.valid;
 339                 case v_int.state is
 340                 when IDLE =>
 341                         if (flush_in = '0') and (d_in.valid = '1') and (d_in.decode.sgl_pipe = '1') then
 342                                 if v_int.outstanding /= 0 then
 343                                         v_int.state := WAIT_FOR_PREV_TO_COMPLETE;
 344                                         stall_out <= '1';
 345                                         is_valid := '0';
 346                                 else
 347                                         -- send insn out and wait on it to complete
 348                                         v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 349                                 end if;
 350                         end if;
 351
 352                 when WAIT_FOR_PREV_TO_COMPLETE =>
 353                         if v_int.outstanding = 0 then
 354                                 -- send insn out and wait on it to complete
 355                                 v_int.state := WAIT_FOR_CURR_TO_COMPLETE;
 356                         else
 357                                 stall_out <= '1';
 358                                 is_valid := '0';
 359                         end if;
 360
 361                 when WAIT_FOR_CURR_TO_COMPLETE =>
 362                         if v_int.outstanding = 0 then
 363                                 v_int.state := IDLE;
 364                         else
 365                                 stall_out <= '1';
 366                                 is_valid := '0';
 367                         end if;
 368                 end case;
 369
 370                 v.e.valid := '0';
 371                 v.m.valid := '0';
 372                 v.l.valid := '0';
 373                 case d_in.decode.unit is
 374                 when ALU =>
 375                         v.e.valid := is_valid;
 376                 when LDST =>
 377                         v.l.valid := is_valid;
 378                 when MUL =>
 379                         v.m.valid := is_valid;
 380                 when NONE =>
 381                         v.e.valid := is_valid;
 382                         v.e.insn_type := OP_ILLEGAL;
 383                 end case;
 384
 385                 if flush_in = '1' then
 386                         v.e.valid := '0';
 387                         v.m.valid := '0';
 388                         v.l.valid := '0';
 389                 end if;
 390
 391                 -- track outstanding instructions
 392                 if v.e.valid = '1' or v.l.valid = '1' or v.m.valid = '1' then
 393                         v_int.outstanding := v_int.outstanding + 1;
 394                 end if;
 395
 396                 assert r_int.outstanding <= 1 report "Outstanding bad " & integer'image(r_int.outstanding) severity failure;
 397
 398                 if rst = '1' then
 399                         v_int.state := IDLE;
 400                         v_int.outstanding := 0;
 401                         v.e := Decode2ToExecute1Init;
 402                         v.l := Decode2ToLoadStore1Init;
 403                         v.m := Decode2ToMultiplyInit;
 404                 end if;
 405
 406                 -- Update registers
 407                 rin <= v;
 408                 rin_int <= v_int;
 409
 410                 -- Update outputs
 411                 e_out <= r.e;
 412                 l_out <= r.l;
 413                 m_out <= r.m;
 414         end process;
 415 end architecture behaviour;