2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * System Console Definition
37 #include "base/inifile.hh"
38 #include "base/str.hh" // for to_number()
39 #include "base/trace.hh"
40 #include "cpu/base_cpu.hh"
41 #include "cpu/exec_context.hh"
42 #include "dev/alpha_console.hh"
43 #include "dev/console.hh"
44 #include "dev/simple_disk.hh"
45 #include "dev/tlaser_clock.hh"
46 #include "mem/bus/bus.hh"
47 #include "mem/bus/pio_interface.hh"
48 #include "mem/bus/pio_interface_impl.hh"
49 #include "mem/functional_mem/memory_control.hh"
50 #include "sim/builder.hh"
51 #include "sim/system.hh"
52 #include "dev/tsunami_io.hh"
53 #include "sim/sim_object.hh"
57 AlphaConsole::AlphaConsole(const string
&name
, SimConsole
*cons
, SimpleDisk
*d
,
58 System
*system
, BaseCPU
*cpu
, SimObject
*clock
,
59 int num_cpus
, MemoryController
*mmu
, Addr a
,
60 HierParams
*hier
, Bus
*bus
)
61 : PioDevice(name
), disk(d
), console(cons
), addr(a
)
63 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
66 pioInterface
= newPioInterface(name
, hier
, bus
, this,
67 &AlphaConsole::cacheAccess
);
68 pioInterface
->addAddrRange(addr
, addr
+ size
);
71 consoleData
= new uint8_t[size
];
72 memset(consoleData
, 0, size
);
74 alphaAccess
->last_offset
= size
- 1;
75 alphaAccess
->kernStart
= system
->getKernelStart();
76 alphaAccess
->kernEnd
= system
->getKernelEnd();
77 alphaAccess
->entryPoint
= system
->getKernelEntry();
79 alphaAccess
->version
= ALPHA_ACCESS_VERSION
;
80 alphaAccess
->numCPUs
= num_cpus
;
81 alphaAccess
->mem_size
= system
->physmem
->size();
82 alphaAccess
->cpuClock
= cpu
->getFreq() / 1000000;
83 TsunamiIO
*clock_linux
= dynamic_cast<TsunamiIO
*>(clock
);
84 TlaserClock
*clock_tru64
= dynamic_cast<TlaserClock
*>(clock
);
86 alphaAccess
->intrClockFrequency
= clock_linux
->frequency();
88 alphaAccess
->intrClockFrequency
= clock_tru64
->frequency();
90 panic("clock must be of type TlaserClock or TsunamiIO\n");
91 alphaAccess
->diskUnit
= 1;
95 AlphaConsole::read(MemReqPtr
&req
, uint8_t *data
)
97 memset(data
, 0, req
->size
);
100 Addr daddr
= req
->paddr
- (addr
& PA_IMPL_MASK
);
103 case offsetof(AlphaAccess
, inputChar
):
104 val
= console
->console_in();
108 val
= *(uint64_t *)(consoleData
+ daddr
);
112 DPRINTF(AlphaConsole
, "read: offset=%#x val=%#x\n", daddr
, val
);
115 case sizeof(uint32_t):
116 *(uint32_t *)data
= (uint32_t)val
;
119 case sizeof(uint64_t):
120 *(uint64_t *)data
= val
;
124 return Machine_Check_Fault
;
132 AlphaConsole::write(MemReqPtr
&req
, const uint8_t *data
)
137 case sizeof(uint32_t):
138 val
= *(uint32_t *)data
;
141 case sizeof(uint64_t):
142 val
= *(uint64_t *)data
;
145 return Machine_Check_Fault
;
148 Addr daddr
= req
->paddr
- (addr
& PA_IMPL_MASK
);
149 ExecContext
*other_xc
;
152 case offsetof(AlphaAccess
, diskUnit
):
153 alphaAccess
->diskUnit
= val
;
156 case offsetof(AlphaAccess
, diskCount
):
157 alphaAccess
->diskCount
= val
;
160 case offsetof(AlphaAccess
, diskPAddr
):
161 alphaAccess
->diskPAddr
= val
;
164 case offsetof(AlphaAccess
, diskBlock
):
165 alphaAccess
->diskBlock
= val
;
168 case offsetof(AlphaAccess
, diskOperation
):
170 disk
->read(alphaAccess
->diskPAddr
, alphaAccess
->diskBlock
,
171 alphaAccess
->diskCount
);
173 panic("Invalid disk operation!");
177 case offsetof(AlphaAccess
, outputChar
):
178 console
->out((char)(val
& 0xff), false);
181 case offsetof(AlphaAccess
, bootStrapImpure
):
182 alphaAccess
->bootStrapImpure
= val
;
185 case offsetof(AlphaAccess
, bootStrapCPU
):
186 warn("%d: Trying to launch another CPU!", curTick
);
187 assert(val
> 0 && "Must not access primary cpu");
189 other_xc
= req
->xc
->system
->execContexts
[val
];
190 other_xc
->regs
.intRegFile
[16] = val
;
191 other_xc
->regs
.ipr
[TheISA::IPR_PALtemp16
] = val
;
192 other_xc
->regs
.intRegFile
[0] = val
;
193 other_xc
->regs
.intRegFile
[30] = alphaAccess
->bootStrapImpure
;
194 other_xc
->activate(); //Start the cpu
198 return Machine_Check_Fault
;
205 AlphaConsole::cacheAccess(MemReqPtr
&req
)
207 return curTick
+ 1000;
211 AlphaAccess::serialize(ostream
&os
)
213 SERIALIZE_SCALAR(last_offset
);
214 SERIALIZE_SCALAR(version
);
215 SERIALIZE_SCALAR(numCPUs
);
216 SERIALIZE_SCALAR(mem_size
);
217 SERIALIZE_SCALAR(cpuClock
);
218 SERIALIZE_SCALAR(intrClockFrequency
);
219 SERIALIZE_SCALAR(kernStart
);
220 SERIALIZE_SCALAR(kernEnd
);
221 SERIALIZE_SCALAR(entryPoint
);
222 SERIALIZE_SCALAR(diskUnit
);
223 SERIALIZE_SCALAR(diskCount
);
224 SERIALIZE_SCALAR(diskPAddr
);
225 SERIALIZE_SCALAR(diskBlock
);
226 SERIALIZE_SCALAR(diskOperation
);
227 SERIALIZE_SCALAR(outputChar
);
228 SERIALIZE_SCALAR(inputChar
);
229 SERIALIZE_SCALAR(bootStrapImpure
);
230 SERIALIZE_SCALAR(bootStrapCPU
);
234 AlphaAccess::unserialize(Checkpoint
*cp
, const std::string
§ion
)
236 UNSERIALIZE_SCALAR(last_offset
);
237 UNSERIALIZE_SCALAR(version
);
238 UNSERIALIZE_SCALAR(numCPUs
);
239 UNSERIALIZE_SCALAR(mem_size
);
240 UNSERIALIZE_SCALAR(cpuClock
);
241 UNSERIALIZE_SCALAR(intrClockFrequency
);
242 UNSERIALIZE_SCALAR(kernStart
);
243 UNSERIALIZE_SCALAR(kernEnd
);
244 UNSERIALIZE_SCALAR(entryPoint
);
245 UNSERIALIZE_SCALAR(diskUnit
);
246 UNSERIALIZE_SCALAR(diskCount
);
247 UNSERIALIZE_SCALAR(diskPAddr
);
248 UNSERIALIZE_SCALAR(diskBlock
);
249 UNSERIALIZE_SCALAR(diskOperation
);
250 UNSERIALIZE_SCALAR(outputChar
);
251 UNSERIALIZE_SCALAR(inputChar
);
252 UNSERIALIZE_SCALAR(bootStrapImpure
);
253 UNSERIALIZE_SCALAR(bootStrapCPU
);
257 AlphaConsole::serialize(ostream
&os
)
259 alphaAccess
->serialize(os
);
263 AlphaConsole::unserialize(Checkpoint
*cp
, const std::string
§ion
)
265 alphaAccess
->unserialize(cp
, section
);
268 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
270 SimObjectParam
<SimConsole
*> sim_console
;
271 SimObjectParam
<SimpleDisk
*> disk
;
273 SimObjectParam
<MemoryController
*> mmu
;
275 SimObjectParam
<System
*> system
;
276 SimObjectParam
<BaseCPU
*> cpu
;
277 SimObjectParam
<SimObject
*> clock
;
278 SimObjectParam
<Bus
*> io_bus
;
279 SimObjectParam
<HierParams
*> hier
;
281 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
283 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
285 INIT_PARAM(sim_console
, "The Simulator Console"),
286 INIT_PARAM(disk
, "Simple Disk"),
287 INIT_PARAM_DFLT(num_cpus
, "Number of CPU's", 1),
288 INIT_PARAM(mmu
, "Memory Controller"),
289 INIT_PARAM(addr
, "Device Address"),
290 INIT_PARAM(system
, "system object"),
291 INIT_PARAM(cpu
, "Processor"),
292 INIT_PARAM(clock
, "Clock"),
293 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
294 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
296 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
298 CREATE_SIM_OBJECT(AlphaConsole
)
300 return new AlphaConsole(getInstanceName(), sim_console
, disk
,
301 system
, cpu
, clock
, num_cpus
, mmu
,
305 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole
)