dev/alpha_console.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * System Console Definition
  31  */
  32
  33 #include <cstddef>
  34 #include <cstdio>
  35 #include <string>
  36
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"  // for to_number()
  39 #include "base/trace.hh"
  40 #include "cpu/base_cpu.hh"
  41 #include "cpu/exec_context.hh"
  42 #include "dev/alpha_console.hh"
  43 #include "dev/console.hh"
  44 #include "dev/simple_disk.hh"
  45 #include "dev/tlaser_clock.hh"
  46 #include "mem/bus/bus.hh"
  47 #include "mem/bus/pio_interface.hh"
  48 #include "mem/bus/pio_interface_impl.hh"
  49 #include "mem/functional_mem/memory_control.hh"
  50 #include "sim/builder.hh"
  51 #include "sim/system.hh"
  52 #include "dev/tsunami_io.hh"
  53 #include "sim/sim_object.hh"
  54
  55 using namespace std;
  56
  57 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
  58                            System *system, BaseCPU *cpu, Platform *platform,
  59                            int num_cpus, MemoryController *mmu, Addr a,
  60                            HierParams *hier, Bus *bus)
  61     : PioDevice(name), disk(d), console(cons), addr(a)
  62 {
  63     mmu->add_child(this, Range<Addr>(addr, addr + size));
  64
  65     if (bus) {
  66         pioInterface = newPioInterface(name, hier, bus, this,
  67                                        &AlphaConsole::cacheAccess);
  68         pioInterface->addAddrRange(addr, addr + size);
  69     }
  70
  71     consoleData = new uint8_t[size];
  72     memset(consoleData, 0, size);
  73
  74     alphaAccess->last_offset = size - 1;
  75     alphaAccess->kernStart = system->getKernelStart();
  76     alphaAccess->kernEnd = system->getKernelEnd();
  77     alphaAccess->entryPoint = system->getKernelEntry();
  78
  79     alphaAccess->version = ALPHA_ACCESS_VERSION;
  80     alphaAccess->numCPUs = num_cpus;
  81     alphaAccess->mem_size = system->physmem->size();
  82     alphaAccess->cpuClock = cpu->getFreq() / 1000000;
  83         alphaAccess->intrClockFrequency = platform->intrFrequency();
  84     alphaAccess->diskUnit = 1;
  85 }
  86
  87 Fault
  88 AlphaConsole::read(MemReqPtr &req, uint8_t *data)
  89 {
  90     memset(data, 0, req->size);
  91     uint64_t val;
  92
  93     Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
  94
  95     switch (daddr) {
  96       case offsetof(AlphaAccess, inputChar):
  97         val = console->console_in();
  98         break;
  99
 100       default:
 101         val = *(uint64_t *)(consoleData + daddr);
 102         break;
 103     }
 104
 105     DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, val);
 106
 107     switch (req->size) {
 108       case sizeof(uint32_t):
 109         *(uint32_t *)data = (uint32_t)val;
 110         break;
 111
 112       case sizeof(uint64_t):
 113         *(uint64_t *)data = val;
 114         break;
 115
 116       default:
 117         return Machine_Check_Fault;
 118     }
 119
 120
 121     return No_Fault;
 122 }
 123
 124 Fault
 125 AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
 126 {
 127     uint64_t val;
 128
 129     switch (req->size) {
 130       case sizeof(uint32_t):
 131         val = *(uint32_t *)data;
 132         break;
 133
 134       case sizeof(uint64_t):
 135         val = *(uint64_t *)data;
 136         break;
 137       default:
 138         return Machine_Check_Fault;
 139     }
 140
 141     Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
 142     ExecContext *other_xc;
 143
 144     switch (daddr) {
 145       case offsetof(AlphaAccess, diskUnit):
 146         alphaAccess->diskUnit = val;
 147         break;
 148
 149       case offsetof(AlphaAccess, diskCount):
 150         alphaAccess->diskCount = val;
 151         break;
 152
 153       case offsetof(AlphaAccess, diskPAddr):
 154         alphaAccess->diskPAddr = val;
 155         break;
 156
 157       case offsetof(AlphaAccess, diskBlock):
 158         alphaAccess->diskBlock = val;
 159         break;
 160
 161       case offsetof(AlphaAccess, diskOperation):
 162         if (val == 0x13)
 163             disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
 164                        alphaAccess->diskCount);
 165         else
 166             panic("Invalid disk operation!");
 167
 168         break;
 169
 170       case offsetof(AlphaAccess, outputChar):
 171         console->out((char)(val & 0xff), false);
 172         break;
 173
 174       case offsetof(AlphaAccess, bootStrapImpure):
 175         alphaAccess->bootStrapImpure = val;
 176         break;
 177
 178       case offsetof(AlphaAccess, bootStrapCPU):
 179         warn("%d: Trying to launch another CPU!", curTick);
 180         assert(val > 0 && "Must not access primary cpu");
 181
 182         other_xc = req->xc->system->execContexts[val];
 183         other_xc->regs.intRegFile[16] = val;
 184         other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
 185         other_xc->regs.intRegFile[0] = val;
 186         other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
 187         other_xc->activate(); //Start the cpu
 188         break;
 189
 190       default:
 191         return Machine_Check_Fault;
 192     }
 193
 194     return No_Fault;
 195 }
 196
 197 Tick
 198 AlphaConsole::cacheAccess(MemReqPtr &req)
 199 {
 200     return curTick + 1000;
 201 }
 202
 203 void
 204 AlphaAccess::serialize(ostream &os)
 205 {
 206     SERIALIZE_SCALAR(last_offset);
 207     SERIALIZE_SCALAR(version);
 208     SERIALIZE_SCALAR(numCPUs);
 209     SERIALIZE_SCALAR(mem_size);
 210     SERIALIZE_SCALAR(cpuClock);
 211     SERIALIZE_SCALAR(intrClockFrequency);
 212     SERIALIZE_SCALAR(kernStart);
 213     SERIALIZE_SCALAR(kernEnd);
 214     SERIALIZE_SCALAR(entryPoint);
 215     SERIALIZE_SCALAR(diskUnit);
 216     SERIALIZE_SCALAR(diskCount);
 217     SERIALIZE_SCALAR(diskPAddr);
 218     SERIALIZE_SCALAR(diskBlock);
 219     SERIALIZE_SCALAR(diskOperation);
 220     SERIALIZE_SCALAR(outputChar);
 221     SERIALIZE_SCALAR(inputChar);
 222     SERIALIZE_SCALAR(bootStrapImpure);
 223     SERIALIZE_SCALAR(bootStrapCPU);
 224 }
 225
 226 void
 227 AlphaAccess::unserialize(Checkpoint *cp, const std::string &section)
 228 {
 229     UNSERIALIZE_SCALAR(last_offset);
 230     UNSERIALIZE_SCALAR(version);
 231     UNSERIALIZE_SCALAR(numCPUs);
 232     UNSERIALIZE_SCALAR(mem_size);
 233     UNSERIALIZE_SCALAR(cpuClock);
 234     UNSERIALIZE_SCALAR(intrClockFrequency);
 235     UNSERIALIZE_SCALAR(kernStart);
 236     UNSERIALIZE_SCALAR(kernEnd);
 237     UNSERIALIZE_SCALAR(entryPoint);
 238     UNSERIALIZE_SCALAR(diskUnit);
 239     UNSERIALIZE_SCALAR(diskCount);
 240     UNSERIALIZE_SCALAR(diskPAddr);
 241     UNSERIALIZE_SCALAR(diskBlock);
 242     UNSERIALIZE_SCALAR(diskOperation);
 243     UNSERIALIZE_SCALAR(outputChar);
 244     UNSERIALIZE_SCALAR(inputChar);
 245     UNSERIALIZE_SCALAR(bootStrapImpure);
 246     UNSERIALIZE_SCALAR(bootStrapCPU);
 247 }
 248
 249 void
 250 AlphaConsole::serialize(ostream &os)
 251 {
 252     alphaAccess->serialize(os);
 253 }
 254
 255 void
 256 AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
 257 {
 258     alphaAccess->unserialize(cp, section);
 259 }
 260
 261 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 262
 263     SimObjectParam<SimConsole *> sim_console;
 264     SimObjectParam<SimpleDisk *> disk;
 265     Param<int> num_cpus;
 266     SimObjectParam<MemoryController *> mmu;
 267     Param<Addr> addr;
 268     SimObjectParam<System *> system;
 269     SimObjectParam<BaseCPU *> cpu;
 270     SimObjectParam<Platform *> platform;
 271     SimObjectParam<Bus*> io_bus;
 272     SimObjectParam<HierParams *> hier;
 273
 274 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 275
 276 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 277
 278     INIT_PARAM(sim_console, "The Simulator Console"),
 279     INIT_PARAM(disk, "Simple Disk"),
 280     INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
 281     INIT_PARAM(mmu, "Memory Controller"),
 282     INIT_PARAM(addr, "Device Address"),
 283     INIT_PARAM(system, "system object"),
 284     INIT_PARAM(cpu, "Processor"),
 285     INIT_PARAM(platform, "platform"),
 286     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 287     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 288
 289 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 290
 291 CREATE_SIM_OBJECT(AlphaConsole)
 292 {
 293     return new AlphaConsole(getInstanceName(), sim_console, disk,
 294                             system, cpu, platform, num_cpus, mmu,
 295                             addr, hier, io_bus);
 296 }
 297
 298 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)