2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * System Console Definition
37 #include "base/inifile.hh"
38 #include "base/str.hh" // for to_number()
39 #include "base/trace.hh"
40 #include "cpu/base_cpu.hh"
41 #include "cpu/exec_context.hh"
42 #include "dev/alpha_console.hh"
43 #include "dev/console.hh"
44 #include "dev/simple_disk.hh"
45 #include "dev/tlaser_clock.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "sim/builder.hh"
48 #include "sim/system.hh"
52 AlphaConsole::AlphaConsole(const string
&name
, SimConsole
*cons
,
53 SimpleDisk
*d
, int size
, System
*system
,
54 BaseCPU
*cpu
, TlaserClock
*clock
, int num_cpus
,
55 Addr addr
, Addr mask
, MemoryController
*mmu
)
56 : MmapDevice(name
, addr
, mask
, mmu
), disk(d
), console(cons
)
58 consoleData
= new uint8_t[size
];
59 memset(consoleData
, 0, size
);
61 alphaAccess
->last_offset
= size
- 1;
62 alphaAccess
->kernStart
= system
->getKernelStart();
63 alphaAccess
->kernEnd
= system
->getKernelEnd();
64 alphaAccess
->entryPoint
= system
->getKernelEntry();
66 alphaAccess
->version
= ALPHA_ACCESS_VERSION
;
67 alphaAccess
->numCPUs
= num_cpus
;
68 alphaAccess
->mem_size
= system
->physmem
->getSize();
69 alphaAccess
->cpuClock
= cpu
->getFreq() / 1000000;
70 alphaAccess
->intrClockFrequency
= clock
->frequency();
72 alphaAccess
->diskUnit
= 1;
76 AlphaConsole::read(MemReqPtr req
, uint8_t *data
)
78 memset(data
, 0, req
->size
);
80 if (req
->size
== sizeof(uint32_t)) {
81 Addr daddr
= req
->paddr
& addr_mask
;
82 *(uint32_t *)data
= *(uint32_t *)(consoleData
+ daddr
);
85 DPRINTF(AlphaConsole
, "read: offset=%#x val=%#x\n",
86 daddr
, *(uint32_t *)data
);
94 AlphaConsole::write(MemReqPtr req
, const uint8_t *data
)
99 case sizeof(uint32_t):
100 val
= *(uint32_t *)data
;
102 case sizeof(uint64_t):
103 val
= *(uint64_t *)data
;
106 return Machine_Check_Fault
;
109 Addr paddr
= req
->paddr
& addr_mask
;
111 if (paddr
== offsetof(AlphaAccess
, diskUnit
)) {
112 alphaAccess
->diskUnit
= val
;
116 if (paddr
== offsetof(AlphaAccess
, diskCount
)) {
117 alphaAccess
->diskCount
= val
;
121 if (paddr
== offsetof(AlphaAccess
, diskPAddr
)) {
122 alphaAccess
->diskPAddr
= val
;
126 if (paddr
== offsetof(AlphaAccess
, diskBlock
)) {
127 alphaAccess
->diskBlock
= val
;
131 if (paddr
== offsetof(AlphaAccess
, diskOperation
)) {
133 disk
->read(alphaAccess
->diskPAddr
, alphaAccess
->diskBlock
,
134 alphaAccess
->diskCount
);
136 panic("Invalid disk operation!");
141 if (paddr
== offsetof(AlphaAccess
, outputChar
)) {
142 console
->out((char)(val
& 0xff), false);
146 if (paddr
== offsetof(AlphaAccess
, bootStrapImpure
)) {
147 alphaAccess
->bootStrapImpure
= val
;
151 if (paddr
== offsetof(AlphaAccess
, bootStrapCPU
)) {
152 warn("%d: Trying to launch another CPU!", curTick
);
154 assert(cpu
> 0 && "Must not access primary cpu");
156 ExecContext
*other_xc
= req
->xc
->system
->execContexts
[cpu
];
157 other_xc
->regs
.intRegFile
[16] = cpu
;
158 other_xc
->regs
.ipr
[TheISA::IPR_PALtemp16
] = cpu
;
159 other_xc
->regs
.intRegFile
[0] = cpu
;
160 other_xc
->regs
.intRegFile
[30] = alphaAccess
->bootStrapImpure
;
161 other_xc
->setStatus(ExecContext::Active
); //Start the cpu
169 AlphaAccess::serialize(ostream
&os
)
171 SERIALIZE_SCALAR(last_offset
);
172 SERIALIZE_SCALAR(version
);
173 SERIALIZE_SCALAR(numCPUs
);
174 SERIALIZE_SCALAR(mem_size
);
175 SERIALIZE_SCALAR(cpuClock
);
176 SERIALIZE_SCALAR(intrClockFrequency
);
177 SERIALIZE_SCALAR(kernStart
);
178 SERIALIZE_SCALAR(kernEnd
);
179 SERIALIZE_SCALAR(entryPoint
);
180 SERIALIZE_SCALAR(diskUnit
);
181 SERIALIZE_SCALAR(diskCount
);
182 SERIALIZE_SCALAR(diskPAddr
);
183 SERIALIZE_SCALAR(diskBlock
);
184 SERIALIZE_SCALAR(diskOperation
);
185 SERIALIZE_SCALAR(outputChar
);
186 SERIALIZE_SCALAR(bootStrapImpure
);
187 SERIALIZE_SCALAR(bootStrapCPU
);
191 AlphaAccess::unserialize(Checkpoint
*cp
, const std::string
§ion
)
193 UNSERIALIZE_SCALAR(last_offset
);
194 UNSERIALIZE_SCALAR(version
);
195 UNSERIALIZE_SCALAR(numCPUs
);
196 UNSERIALIZE_SCALAR(mem_size
);
197 UNSERIALIZE_SCALAR(cpuClock
);
198 UNSERIALIZE_SCALAR(intrClockFrequency
);
199 UNSERIALIZE_SCALAR(kernStart
);
200 UNSERIALIZE_SCALAR(kernEnd
);
201 UNSERIALIZE_SCALAR(entryPoint
);
202 UNSERIALIZE_SCALAR(diskUnit
);
203 UNSERIALIZE_SCALAR(diskCount
);
204 UNSERIALIZE_SCALAR(diskPAddr
);
205 UNSERIALIZE_SCALAR(diskBlock
);
206 UNSERIALIZE_SCALAR(diskOperation
);
207 UNSERIALIZE_SCALAR(outputChar
);
208 UNSERIALIZE_SCALAR(bootStrapImpure
);
209 UNSERIALIZE_SCALAR(bootStrapCPU
);
213 AlphaConsole::serialize(ostream
&os
)
215 alphaAccess
->serialize(os
);
219 AlphaConsole::unserialize(Checkpoint
*cp
, const std::string
§ion
)
221 alphaAccess
->unserialize(cp
, section
);
224 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
226 SimObjectParam
<SimConsole
*> sim_console
;
227 SimObjectParam
<SimpleDisk
*> disk
;
230 SimObjectParam
<MemoryController
*> mmu
;
233 SimObjectParam
<System
*> system
;
234 SimObjectParam
<BaseCPU
*> cpu
;
235 SimObjectParam
<TlaserClock
*> clock
;
237 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
239 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
241 INIT_PARAM(sim_console
, "The Simulator Console"),
242 INIT_PARAM(disk
, "Simple Disk"),
243 INIT_PARAM_DFLT(size
, "AlphaConsole size", sizeof(AlphaAccess
)),
244 INIT_PARAM_DFLT(num_cpus
, "Number of CPU's", 1),
245 INIT_PARAM(mmu
, "Memory Controller"),
246 INIT_PARAM(addr
, "Device Address"),
247 INIT_PARAM(mask
, "Address Mask"),
248 INIT_PARAM(system
, "system object"),
249 INIT_PARAM(cpu
, "Processor"),
250 INIT_PARAM(clock
, "Turbolaser Clock")
252 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
254 CREATE_SIM_OBJECT(AlphaConsole
)
256 return new AlphaConsole(getInstanceName(), sim_console
,
258 cpu
, clock
, num_cpus
,
262 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole
)