2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * System Console Definition
37 #include "base/inifile.hh"
38 #include "base/str.hh" // for to_number()
39 #include "base/trace.hh"
40 #include "cpu/base_cpu.hh"
41 #include "cpu/exec_context.hh"
42 #include "dev/alpha_console.hh"
43 #include "dev/simconsole.hh"
44 #include "dev/simple_disk.hh"
45 #include "dev/tlaser_clock.hh"
46 #include "mem/bus/bus.hh"
47 #include "mem/bus/pio_interface.hh"
48 #include "mem/bus/pio_interface_impl.hh"
49 #include "mem/functional_mem/memory_control.hh"
50 #include "sim/builder.hh"
51 #include "sim/system.hh"
52 #include "dev/tsunami_io.hh"
53 #include "sim/sim_object.hh"
54 #include "targetarch/byte_swap.hh"
58 AlphaConsole::AlphaConsole(const string
&name
, SimConsole
*cons
, SimpleDisk
*d
,
59 System
*system
, BaseCPU
*cpu
, Platform
*platform
,
60 int num_cpus
, MemoryController
*mmu
, Addr a
,
61 HierParams
*hier
, Bus
*bus
)
62 : PioDevice(name
), disk(d
), console(cons
), addr(a
)
64 mmu
->add_child(this, RangeSize(addr
, size
));
67 pioInterface
= newPioInterface(name
, hier
, bus
, this,
68 &AlphaConsole::cacheAccess
);
69 pioInterface
->addAddrRange(RangeSize(addr
, size
));
72 alphaAccess
= new AlphaAccess
;
73 alphaAccess
->last_offset
= size
- 1;
74 alphaAccess
->kernStart
= system
->getKernelStart();
75 alphaAccess
->kernEnd
= system
->getKernelEnd();
76 alphaAccess
->entryPoint
= system
->getKernelEntry();
78 alphaAccess
->version
= ALPHA_ACCESS_VERSION
;
79 alphaAccess
->numCPUs
= num_cpus
;
80 alphaAccess
->mem_size
= system
->physmem
->size();
81 alphaAccess
->cpuClock
= cpu
->getFreq() / 1000000;
82 alphaAccess
->intrClockFrequency
= platform
->intrFrequency();
83 alphaAccess
->diskUnit
= 1;
85 alphaAccess
->diskCount
= 0;
86 alphaAccess
->diskPAddr
= 0;
87 alphaAccess
->diskBlock
= 0;
88 alphaAccess
->diskOperation
= 0;
89 alphaAccess
->outputChar
= 0;
90 alphaAccess
->inputChar
= 0;
91 alphaAccess
->bootStrapImpure
= 0;
92 alphaAccess
->bootStrapCPU
= 0;
93 alphaAccess
->align2
= 0;
97 AlphaConsole::read(MemReqPtr
&req
, uint8_t *data
)
99 memset(data
, 0, req
->size
);
101 Addr daddr
= req
->paddr
- (addr
& EV5::PAddrImplMask
);
105 case sizeof(uint32_t):
106 DPRINTF(AlphaConsole
, "read: offset=%#x val=%#x\n", daddr
, *(uint32_t*)data
);
109 case offsetof(AlphaAccess
, last_offset
):
110 *(uint32_t*)data
= alphaAccess
->last_offset
;
112 case offsetof(AlphaAccess
, version
):
113 *(uint32_t*)data
= alphaAccess
->version
;
115 case offsetof(AlphaAccess
, numCPUs
):
116 *(uint32_t*)data
= alphaAccess
->numCPUs
;
118 case offsetof(AlphaAccess
, bootStrapCPU
):
119 *(uint32_t*)data
= alphaAccess
->bootStrapCPU
;
121 case offsetof(AlphaAccess
, intrClockFrequency
):
122 *(uint32_t*)data
= alphaAccess
->intrClockFrequency
;
125 // Old console code read in everyting as a 32bit int
126 *(uint32_t*)data
= *(uint32_t*)(consoleData
+ daddr
);
130 case sizeof(uint64_t):
131 DPRINTF(AlphaConsole
, "read: offset=%#x val=%#x\n", daddr
, *(uint64_t*)data
);
134 case offsetof(AlphaAccess
, inputChar
):
135 *(uint64_t*)data
= console
->console_in();
137 case offsetof(AlphaAccess
, cpuClock
):
138 *(uint64_t*)data
= alphaAccess
->cpuClock
;
140 case offsetof(AlphaAccess
, mem_size
):
141 *(uint64_t*)data
= alphaAccess
->mem_size
;
143 case offsetof(AlphaAccess
, kernStart
):
144 *(uint64_t*)data
= alphaAccess
->kernStart
;
146 case offsetof(AlphaAccess
, kernEnd
):
147 *(uint64_t*)data
= alphaAccess
->kernEnd
;
149 case offsetof(AlphaAccess
, entryPoint
):
150 *(uint64_t*)data
= alphaAccess
->entryPoint
;
152 case offsetof(AlphaAccess
, diskUnit
):
153 *(uint64_t*)data
= alphaAccess
->diskUnit
;
155 case offsetof(AlphaAccess
, diskCount
):
156 *(uint64_t*)data
= alphaAccess
->diskCount
;
158 case offsetof(AlphaAccess
, diskPAddr
):
159 *(uint64_t*)data
= alphaAccess
->diskPAddr
;
161 case offsetof(AlphaAccess
, diskBlock
):
162 *(uint64_t*)data
= alphaAccess
->diskBlock
;
164 case offsetof(AlphaAccess
, diskOperation
):
165 *(uint64_t*)data
= alphaAccess
->diskOperation
;
167 case offsetof(AlphaAccess
, outputChar
):
168 *(uint64_t*)data
= alphaAccess
->outputChar
;
170 case offsetof(AlphaAccess
, bootStrapImpure
):
171 *(uint64_t*)data
= alphaAccess
->bootStrapImpure
;
174 panic("Unknown 64bit access, %#x\n", daddr
);
178 return Machine_Check_Fault
;
185 AlphaConsole::write(MemReqPtr
&req
, const uint8_t *data
)
190 case sizeof(uint32_t):
191 val
= *(uint32_t *)data
;
194 case sizeof(uint64_t):
195 val
= *(uint64_t *)data
;
198 return Machine_Check_Fault
;
201 Addr daddr
= req
->paddr
- (addr
& EV5::PAddrImplMask
);
202 ExecContext
*other_xc
;
205 case offsetof(AlphaAccess
, diskUnit
):
206 alphaAccess
->diskUnit
= val
;
209 case offsetof(AlphaAccess
, diskCount
):
210 alphaAccess
->diskCount
= val
;
213 case offsetof(AlphaAccess
, diskPAddr
):
214 alphaAccess
->diskPAddr
= val
;
217 case offsetof(AlphaAccess
, diskBlock
):
218 alphaAccess
->diskBlock
= val
;
221 case offsetof(AlphaAccess
, diskOperation
):
223 disk
->read(alphaAccess
->diskPAddr
, alphaAccess
->diskBlock
,
224 alphaAccess
->diskCount
);
226 panic("Invalid disk operation!");
230 case offsetof(AlphaAccess
, outputChar
):
231 console
->out((char)(val
& 0xff));
234 case offsetof(AlphaAccess
, bootStrapImpure
):
235 alphaAccess
->bootStrapImpure
= val
;
238 case offsetof(AlphaAccess
, bootStrapCPU
):
239 warn("%d: Trying to launch another CPU!", curTick
);
240 assert(val
> 0 && "Must not access primary cpu");
242 other_xc
= req
->xc
->system
->execContexts
[val
];
243 other_xc
->regs
.intRegFile
[16] = val
;
244 other_xc
->regs
.ipr
[TheISA::IPR_PALtemp16
] = val
;
245 other_xc
->regs
.intRegFile
[0] = val
;
246 other_xc
->regs
.intRegFile
[30] = alphaAccess
->bootStrapImpure
;
247 other_xc
->activate(); //Start the cpu
251 return Machine_Check_Fault
;
258 AlphaConsole::cacheAccess(MemReqPtr
&req
)
260 return curTick
+ 1000;
264 AlphaAccess::serialize(ostream
&os
)
266 SERIALIZE_SCALAR(last_offset
);
267 SERIALIZE_SCALAR(version
);
268 SERIALIZE_SCALAR(numCPUs
);
269 SERIALIZE_SCALAR(mem_size
);
270 SERIALIZE_SCALAR(cpuClock
);
271 SERIALIZE_SCALAR(intrClockFrequency
);
272 SERIALIZE_SCALAR(kernStart
);
273 SERIALIZE_SCALAR(kernEnd
);
274 SERIALIZE_SCALAR(entryPoint
);
275 SERIALIZE_SCALAR(diskUnit
);
276 SERIALIZE_SCALAR(diskCount
);
277 SERIALIZE_SCALAR(diskPAddr
);
278 SERIALIZE_SCALAR(diskBlock
);
279 SERIALIZE_SCALAR(diskOperation
);
280 SERIALIZE_SCALAR(outputChar
);
281 SERIALIZE_SCALAR(inputChar
);
282 SERIALIZE_SCALAR(bootStrapImpure
);
283 SERIALIZE_SCALAR(bootStrapCPU
);
287 AlphaAccess::unserialize(Checkpoint
*cp
, const std::string
§ion
)
289 UNSERIALIZE_SCALAR(last_offset
);
290 UNSERIALIZE_SCALAR(version
);
291 UNSERIALIZE_SCALAR(numCPUs
);
292 UNSERIALIZE_SCALAR(mem_size
);
293 UNSERIALIZE_SCALAR(cpuClock
);
294 UNSERIALIZE_SCALAR(intrClockFrequency
);
295 UNSERIALIZE_SCALAR(kernStart
);
296 UNSERIALIZE_SCALAR(kernEnd
);
297 UNSERIALIZE_SCALAR(entryPoint
);
298 UNSERIALIZE_SCALAR(diskUnit
);
299 UNSERIALIZE_SCALAR(diskCount
);
300 UNSERIALIZE_SCALAR(diskPAddr
);
301 UNSERIALIZE_SCALAR(diskBlock
);
302 UNSERIALIZE_SCALAR(diskOperation
);
303 UNSERIALIZE_SCALAR(outputChar
);
304 UNSERIALIZE_SCALAR(inputChar
);
305 UNSERIALIZE_SCALAR(bootStrapImpure
);
306 UNSERIALIZE_SCALAR(bootStrapCPU
);
310 AlphaConsole::serialize(ostream
&os
)
312 alphaAccess
->serialize(os
);
316 AlphaConsole::unserialize(Checkpoint
*cp
, const std::string
§ion
)
318 alphaAccess
->unserialize(cp
, section
);
321 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
323 SimObjectParam
<SimConsole
*> sim_console
;
324 SimObjectParam
<SimpleDisk
*> disk
;
326 SimObjectParam
<MemoryController
*> mmu
;
328 SimObjectParam
<System
*> system
;
329 SimObjectParam
<BaseCPU
*> cpu
;
330 SimObjectParam
<Platform
*> platform
;
331 SimObjectParam
<Bus
*> io_bus
;
332 SimObjectParam
<HierParams
*> hier
;
334 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole
)
336 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
338 INIT_PARAM(sim_console
, "The Simulator Console"),
339 INIT_PARAM(disk
, "Simple Disk"),
340 INIT_PARAM_DFLT(num_cpus
, "Number of CPU's", 1),
341 INIT_PARAM(mmu
, "Memory Controller"),
342 INIT_PARAM(addr
, "Device Address"),
343 INIT_PARAM(system
, "system object"),
344 INIT_PARAM(cpu
, "Processor"),
345 INIT_PARAM(platform
, "platform"),
346 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
347 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
349 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole
)
351 CREATE_SIM_OBJECT(AlphaConsole
)
353 return new AlphaConsole(getInstanceName(), sim_console
, disk
,
354 system
, cpu
, platform
, num_cpus
, mmu
,
358 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole
)