dev/alpha_console.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * System Console Definition
  31  */
  32
  33 #include <cstddef>
  34 #include <cstdio>
  35 #include <string>
  36
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"  // for to_number()
  39 #include "base/trace.hh"
  40 #include "cpu/base_cpu.hh"
  41 #include "cpu/exec_context.hh"
  42 #include "dev/alpha_console.hh"
  43 #include "dev/console.hh"
  44 #include "dev/simple_disk.hh"
  45 #include "dev/tlaser_clock.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/system.hh"
  49 #include "dev/tsunami_io.hh"
  50
  51 using namespace std;
  52
  53 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
  54                            SimpleDisk *d, int size, System *system,
  55                            BaseCPU *cpu, TsunamiIO *clock, int num_cpus,
  56                            Addr addr, Addr mask, MemoryController *mmu)
  57     : MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
  58 {
  59     consoleData = new uint8_t[size];
  60     memset(consoleData, 0, size);
  61
  62     alphaAccess->last_offset = size - 1;
  63     alphaAccess->kernStart = system->getKernelStart();
  64     alphaAccess->kernEnd = system->getKernelEnd();
  65     alphaAccess->entryPoint = system->getKernelEntry();
  66
  67     alphaAccess->version = ALPHA_ACCESS_VERSION;
  68     alphaAccess->numCPUs = num_cpus;
  69     alphaAccess->mem_size = system->physmem->getSize();
  70     alphaAccess->cpuClock = cpu->getFreq() / 1000000;
  71     alphaAccess->intrClockFrequency = clock->frequency();
  72
  73     alphaAccess->diskUnit = 1;
  74 }
  75
  76 Fault
  77 AlphaConsole::read(MemReqPtr &req, uint8_t *data)
  78 {
  79     memset(data, 0, req->size);
  80     uint64_t val;
  81
  82     Addr daddr = req->paddr & addr_mask;
  83     switch (daddr) {
  84       case offsetof(AlphaAccess, inputChar):
  85         val = console->console_in();
  86         break;
  87
  88       default:
  89         val = *(uint64_t *)(consoleData + daddr);
  90         break;
  91     }
  92
  93     DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, val);
  94
  95     switch (req->size) {
  96       case sizeof(uint32_t):
  97         *(uint32_t *)data = (uint32_t)val;
  98         break;
  99
 100       case sizeof(uint64_t):
 101         *(uint64_t *)data = val;
 102         break;
 103
 104       default:
 105         return Machine_Check_Fault;
 106     }
 107
 108
 109     return No_Fault;
 110 }
 111
 112 Fault
 113 AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
 114 {
 115     uint64_t val;
 116
 117     switch (req->size) {
 118       case sizeof(uint32_t):
 119         val = *(uint32_t *)data;
 120         break;
 121
 122       case sizeof(uint64_t):
 123         val = *(uint64_t *)data;
 124         break;
 125       default:
 126         return Machine_Check_Fault;
 127     }
 128
 129     Addr daddr = req->paddr & addr_mask;
 130     ExecContext *other_xc;
 131
 132     switch (daddr) {
 133       case offsetof(AlphaAccess, diskUnit):
 134         alphaAccess->diskUnit = val;
 135         break;
 136
 137       case offsetof(AlphaAccess, diskCount):
 138         alphaAccess->diskCount = val;
 139         break;
 140
 141       case offsetof(AlphaAccess, diskPAddr):
 142         alphaAccess->diskPAddr = val;
 143         break;
 144
 145       case offsetof(AlphaAccess, diskBlock):
 146         alphaAccess->diskBlock = val;
 147         break;
 148
 149       case offsetof(AlphaAccess, diskOperation):
 150         if (val == 0x13)
 151             disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
 152                        alphaAccess->diskCount);
 153         else
 154             panic("Invalid disk operation!");
 155
 156         break;
 157
 158       case offsetof(AlphaAccess, outputChar):
 159         console->out((char)(val & 0xff), false);
 160         break;
 161
 162       case offsetof(AlphaAccess, bootStrapImpure):
 163         alphaAccess->bootStrapImpure = val;
 164         break;
 165
 166       case offsetof(AlphaAccess, bootStrapCPU):
 167         warn("%d: Trying to launch another CPU!", curTick);
 168         assert(val > 0 && "Must not access primary cpu");
 169
 170         other_xc = req->xc->system->execContexts[val];
 171         other_xc->regs.intRegFile[16] = val;
 172         other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
 173         other_xc->regs.intRegFile[0] = val;
 174         other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
 175         other_xc->activate(); //Start the cpu
 176         break;
 177
 178       default:
 179         return Machine_Check_Fault;
 180     }
 181
 182     return No_Fault;
 183 }
 184
 185 void
 186 AlphaAccess::serialize(ostream &os)
 187 {
 188     SERIALIZE_SCALAR(last_offset);
 189     SERIALIZE_SCALAR(version);
 190     SERIALIZE_SCALAR(numCPUs);
 191     SERIALIZE_SCALAR(mem_size);
 192     SERIALIZE_SCALAR(cpuClock);
 193     SERIALIZE_SCALAR(intrClockFrequency);
 194     SERIALIZE_SCALAR(kernStart);
 195     SERIALIZE_SCALAR(kernEnd);
 196     SERIALIZE_SCALAR(entryPoint);
 197     SERIALIZE_SCALAR(diskUnit);
 198     SERIALIZE_SCALAR(diskCount);
 199     SERIALIZE_SCALAR(diskPAddr);
 200     SERIALIZE_SCALAR(diskBlock);
 201     SERIALIZE_SCALAR(diskOperation);
 202     SERIALIZE_SCALAR(outputChar);
 203     SERIALIZE_SCALAR(inputChar);
 204     SERIALIZE_SCALAR(bootStrapImpure);
 205     SERIALIZE_SCALAR(bootStrapCPU);
 206 }
 207
 208 void
 209 AlphaAccess::unserialize(Checkpoint *cp, const std::string &section)
 210 {
 211     UNSERIALIZE_SCALAR(last_offset);
 212     UNSERIALIZE_SCALAR(version);
 213     UNSERIALIZE_SCALAR(numCPUs);
 214     UNSERIALIZE_SCALAR(mem_size);
 215     UNSERIALIZE_SCALAR(cpuClock);
 216     UNSERIALIZE_SCALAR(intrClockFrequency);
 217     UNSERIALIZE_SCALAR(kernStart);
 218     UNSERIALIZE_SCALAR(kernEnd);
 219     UNSERIALIZE_SCALAR(entryPoint);
 220     UNSERIALIZE_SCALAR(diskUnit);
 221     UNSERIALIZE_SCALAR(diskCount);
 222     UNSERIALIZE_SCALAR(diskPAddr);
 223     UNSERIALIZE_SCALAR(diskBlock);
 224     UNSERIALIZE_SCALAR(diskOperation);
 225     UNSERIALIZE_SCALAR(outputChar);
 226     UNSERIALIZE_SCALAR(inputChar);
 227     UNSERIALIZE_SCALAR(bootStrapImpure);
 228     UNSERIALIZE_SCALAR(bootStrapCPU);
 229 }
 230
 231 void
 232 AlphaConsole::serialize(ostream &os)
 233 {
 234     alphaAccess->serialize(os);
 235 }
 236
 237 void
 238 AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
 239 {
 240     alphaAccess->unserialize(cp, section);
 241 }
 242
 243 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 244
 245     SimObjectParam<SimConsole *> sim_console;
 246     SimObjectParam<SimpleDisk *> disk;
 247     Param<int> size;
 248     Param<int> num_cpus;
 249     SimObjectParam<MemoryController *> mmu;
 250     Param<Addr> addr;
 251     Param<Addr> mask;
 252     SimObjectParam<System *> system;
 253     SimObjectParam<BaseCPU *> cpu;
 254     SimObjectParam<TsunamiIO *> clock;
 255
 256 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 257
 258 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 259
 260     INIT_PARAM(sim_console, "The Simulator Console"),
 261     INIT_PARAM(disk, "Simple Disk"),
 262     INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)),
 263     INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
 264     INIT_PARAM(mmu, "Memory Controller"),
 265     INIT_PARAM(addr, "Device Address"),
 266     INIT_PARAM(mask, "Address Mask"),
 267     INIT_PARAM(system, "system object"),
 268     INIT_PARAM(cpu, "Processor"),
 269     INIT_PARAM(clock, "Turbolaser Clock")
 270
 271 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 272
 273 CREATE_SIM_OBJECT(AlphaConsole)
 274 {
 275     return  new AlphaConsole(getInstanceName(), sim_console,
 276                              disk, size, system,
 277                              cpu, clock, num_cpus,
 278                              addr, mask, mmu);
 279 }
 280
 281 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)