dev/alpha_console.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * System Console Definition
  31  */
  32
  33 #include <cstddef>
  34 #include <cstdio>
  35 #include <string>
  36
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"  // for to_number()
  39 #include "base/trace.hh"
  40 #include "cpu/base_cpu.hh"
  41 #include "cpu/exec_context.hh"
  42 #include "dev/alpha_console.hh"
  43 #include "dev/console.hh"
  44 #include "dev/simple_disk.hh"
  45 #include "dev/tlaser_clock.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/system.hh"
  49 #include "dev/tsunami_io.hh"
  50
  51 using namespace std;
  52
  53 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
  54                            SimpleDisk *d, System *system,
  55                            BaseCPU *cpu, TsunamiIO *clock, int num_cpus,
  56                            Addr a, MemoryController *mmu)
  57     : FunctionalMemory(name), disk(d), console(cons), addr(a)
  58 {
  59     mmu->add_child(this, Range<Addr>(addr, addr + size));
  60
  61     consoleData = new uint8_t[size];
  62     memset(consoleData, 0, size);
  63
  64     alphaAccess->last_offset = size - 1;
  65     alphaAccess->kernStart = system->getKernelStart();
  66     alphaAccess->kernEnd = system->getKernelEnd();
  67     alphaAccess->entryPoint = system->getKernelEntry();
  68
  69     alphaAccess->version = ALPHA_ACCESS_VERSION;
  70     alphaAccess->numCPUs = num_cpus;
  71     alphaAccess->mem_size = system->physmem->size();
  72     alphaAccess->cpuClock = cpu->getFreq() / 1000000;
  73     alphaAccess->intrClockFrequency = clock->frequency();
  74
  75     alphaAccess->diskUnit = 1;
  76 }
  77
  78 Fault
  79 AlphaConsole::read(MemReqPtr &req, uint8_t *data)
  80 {
  81     memset(data, 0, req->size);
  82     uint64_t val;
  83
  84     Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
  85
  86     switch (daddr) {
  87       case offsetof(AlphaAccess, inputChar):
  88         val = console->console_in();
  89         break;
  90
  91       default:
  92         val = *(uint64_t *)(consoleData + daddr);
  93         break;
  94     }
  95
  96     DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, val);
  97
  98     switch (req->size) {
  99       case sizeof(uint32_t):
 100         *(uint32_t *)data = (uint32_t)val;
 101         break;
 102
 103       case sizeof(uint64_t):
 104         *(uint64_t *)data = val;
 105         break;
 106
 107       default:
 108         return Machine_Check_Fault;
 109     }
 110
 111
 112     return No_Fault;
 113 }
 114
 115 Fault
 116 AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
 117 {
 118     uint64_t val;
 119
 120     switch (req->size) {
 121       case sizeof(uint32_t):
 122         val = *(uint32_t *)data;
 123         break;
 124
 125       case sizeof(uint64_t):
 126         val = *(uint64_t *)data;
 127         break;
 128       default:
 129         return Machine_Check_Fault;
 130     }
 131
 132     Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
 133     ExecContext *other_xc;
 134
 135     switch (daddr) {
 136       case offsetof(AlphaAccess, diskUnit):
 137         alphaAccess->diskUnit = val;
 138         break;
 139
 140       case offsetof(AlphaAccess, diskCount):
 141         alphaAccess->diskCount = val;
 142         break;
 143
 144       case offsetof(AlphaAccess, diskPAddr):
 145         alphaAccess->diskPAddr = val;
 146         break;
 147
 148       case offsetof(AlphaAccess, diskBlock):
 149         alphaAccess->diskBlock = val;
 150         break;
 151
 152       case offsetof(AlphaAccess, diskOperation):
 153         if (val == 0x13)
 154             disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
 155                        alphaAccess->diskCount);
 156         else
 157             panic("Invalid disk operation!");
 158
 159         break;
 160
 161       case offsetof(AlphaAccess, outputChar):
 162         console->out((char)(val & 0xff), false);
 163         break;
 164
 165       case offsetof(AlphaAccess, bootStrapImpure):
 166         alphaAccess->bootStrapImpure = val;
 167         break;
 168
 169       case offsetof(AlphaAccess, bootStrapCPU):
 170         warn("%d: Trying to launch another CPU!", curTick);
 171         assert(val > 0 && "Must not access primary cpu");
 172
 173         other_xc = req->xc->system->execContexts[val];
 174         other_xc->regs.intRegFile[16] = val;
 175         other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
 176         other_xc->regs.intRegFile[0] = val;
 177         other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
 178         other_xc->activate(); //Start the cpu
 179         break;
 180
 181       default:
 182         return Machine_Check_Fault;
 183     }
 184
 185     return No_Fault;
 186 }
 187
 188 void
 189 AlphaAccess::serialize(ostream &os)
 190 {
 191     SERIALIZE_SCALAR(last_offset);
 192     SERIALIZE_SCALAR(version);
 193     SERIALIZE_SCALAR(numCPUs);
 194     SERIALIZE_SCALAR(mem_size);
 195     SERIALIZE_SCALAR(cpuClock);
 196     SERIALIZE_SCALAR(intrClockFrequency);
 197     SERIALIZE_SCALAR(kernStart);
 198     SERIALIZE_SCALAR(kernEnd);
 199     SERIALIZE_SCALAR(entryPoint);
 200     SERIALIZE_SCALAR(diskUnit);
 201     SERIALIZE_SCALAR(diskCount);
 202     SERIALIZE_SCALAR(diskPAddr);
 203     SERIALIZE_SCALAR(diskBlock);
 204     SERIALIZE_SCALAR(diskOperation);
 205     SERIALIZE_SCALAR(outputChar);
 206     SERIALIZE_SCALAR(inputChar);
 207     SERIALIZE_SCALAR(bootStrapImpure);
 208     SERIALIZE_SCALAR(bootStrapCPU);
 209 }
 210
 211 void
 212 AlphaAccess::unserialize(Checkpoint *cp, const std::string &section)
 213 {
 214     UNSERIALIZE_SCALAR(last_offset);
 215     UNSERIALIZE_SCALAR(version);
 216     UNSERIALIZE_SCALAR(numCPUs);
 217     UNSERIALIZE_SCALAR(mem_size);
 218     UNSERIALIZE_SCALAR(cpuClock);
 219     UNSERIALIZE_SCALAR(intrClockFrequency);
 220     UNSERIALIZE_SCALAR(kernStart);
 221     UNSERIALIZE_SCALAR(kernEnd);
 222     UNSERIALIZE_SCALAR(entryPoint);
 223     UNSERIALIZE_SCALAR(diskUnit);
 224     UNSERIALIZE_SCALAR(diskCount);
 225     UNSERIALIZE_SCALAR(diskPAddr);
 226     UNSERIALIZE_SCALAR(diskBlock);
 227     UNSERIALIZE_SCALAR(diskOperation);
 228     UNSERIALIZE_SCALAR(outputChar);
 229     UNSERIALIZE_SCALAR(inputChar);
 230     UNSERIALIZE_SCALAR(bootStrapImpure);
 231     UNSERIALIZE_SCALAR(bootStrapCPU);
 232 }
 233
 234 void
 235 AlphaConsole::serialize(ostream &os)
 236 {
 237     alphaAccess->serialize(os);
 238 }
 239
 240 void
 241 AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
 242 {
 243     alphaAccess->unserialize(cp, section);
 244 }
 245
 246 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 247
 248     SimObjectParam<SimConsole *> sim_console;
 249     SimObjectParam<SimpleDisk *> disk;
 250     Param<int> num_cpus;
 251     SimObjectParam<MemoryController *> mmu;
 252     Param<Addr> addr;
 253     SimObjectParam<System *> system;
 254     SimObjectParam<BaseCPU *> cpu;
 255     SimObjectParam<TsunamiIO *> clock;
 256
 257 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 258
 259 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 260
 261     INIT_PARAM(sim_console, "The Simulator Console"),
 262     INIT_PARAM(disk, "Simple Disk"),
 263     INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
 264     INIT_PARAM(mmu, "Memory Controller"),
 265     INIT_PARAM(addr, "Device Address"),
 266     INIT_PARAM(system, "system object"),
 267     INIT_PARAM(cpu, "Processor"),
 268     INIT_PARAM(clock, "Turbolaser Clock")
 269
 270 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 271
 272 CREATE_SIM_OBJECT(AlphaConsole)
 273 {
 274     return  new AlphaConsole(getInstanceName(), sim_console, disk,
 275                              system, cpu, clock, num_cpus, addr, mmu);
 276 }
 277
 278 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)