dev/alpha_console.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * System Console Definition
  31  */
  32
  33 #include <cstddef>
  34 #include <cstdio>
  35 #include <string>
  36
  37 #include "base/inifile.hh"
  38 #include "base/str.hh"  // for to_number()
  39 #include "base/trace.hh"
  40 #include "cpu/base_cpu.hh"
  41 #include "cpu/exec_context.hh"
  42 #include "dev/alpha_console.hh"
  43 #include "dev/console.hh"
  44 #include "dev/simple_disk.hh"
  45 #include "dev/tlaser_clock.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/system.hh"
  49
  50 using namespace std;
  51
  52 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
  53                            SimpleDisk *d, int size, System *system,
  54                            BaseCPU *cpu, TlaserClock *clock, int num_cpus,
  55                            Addr addr, Addr mask, MemoryController *mmu)
  56     : MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
  57 {
  58     consoleData = new uint8_t[size];
  59     memset(consoleData, 0, size);
  60
  61     alphaAccess->last_offset = size - 1;
  62     alphaAccess->kernStart = system->getKernelStart();
  63     alphaAccess->kernEnd = system->getKernelEnd();
  64     alphaAccess->entryPoint = system->getKernelEntry();
  65
  66     alphaAccess->version = ALPHA_ACCESS_VERSION;
  67     alphaAccess->numCPUs = num_cpus;
  68     alphaAccess->mem_size = system->physmem->getSize();
  69     alphaAccess->cpuClock = cpu->getFreq() / 1000000;
  70     alphaAccess->intrClockFrequency = clock->frequency();
  71
  72     alphaAccess->diskUnit = 1;
  73 }
  74
  75 Fault
  76 AlphaConsole::read(MemReqPtr req, uint8_t *data)
  77 {
  78     memset(data, 0, req->size);
  79
  80     if (req->size == sizeof(uint32_t)) {
  81         Addr daddr = req->paddr & addr_mask;
  82         *(uint32_t *)data = *(uint32_t *)(consoleData + daddr);
  83
  84 #if 0
  85         DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n",
  86                 daddr, *(uint32_t *)data);
  87 #endif
  88     }
  89
  90     return No_Fault;
  91 }
  92
  93 Fault
  94 AlphaConsole::write(MemReqPtr req, const uint8_t *data)
  95 {
  96     uint64_t val;
  97
  98     switch (req->size) {
  99       case sizeof(uint32_t):
 100         val = *(uint32_t *)data;
 101         break;
 102       case sizeof(uint64_t):
 103         val = *(uint64_t *)data;
 104         break;
 105       default:
 106         return Machine_Check_Fault;
 107     }
 108
 109     Addr paddr = req->paddr & addr_mask;
 110
 111     if (paddr == offsetof(AlphaAccess, diskUnit)) {
 112         alphaAccess->diskUnit = val;
 113         return No_Fault;
 114     }
 115
 116     if (paddr == offsetof(AlphaAccess, diskCount)) {
 117         alphaAccess->diskCount = val;
 118         return No_Fault;
 119     }
 120
 121     if (paddr == offsetof(AlphaAccess, diskPAddr)) {
 122         alphaAccess->diskPAddr = val;
 123         return No_Fault;
 124     }
 125
 126     if (paddr == offsetof(AlphaAccess, diskBlock)) {
 127         alphaAccess->diskBlock = val;
 128         return No_Fault;
 129     }
 130
 131     if (paddr == offsetof(AlphaAccess, diskOperation)) {
 132         if (val == 0x13)
 133             disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
 134                        alphaAccess->diskCount);
 135         else
 136             panic("Invalid disk operation!");
 137
 138         return No_Fault;
 139     }
 140
 141     if (paddr == offsetof(AlphaAccess, outputChar)) {
 142         console->out((char)(val & 0xff), false);
 143         return No_Fault;
 144     }
 145
 146     if (paddr == offsetof(AlphaAccess, bootStrapImpure)) {
 147         alphaAccess->bootStrapImpure = val;
 148         return No_Fault;
 149     }
 150
 151     if (paddr == offsetof(AlphaAccess, bootStrapCPU)) {
 152         warn("%d: Trying to launch another CPU!", curTick);
 153         int cpu = val;
 154         assert(cpu > 0 && "Must not access primary cpu");
 155
 156         ExecContext *other_xc = req->xc->system->execContexts[cpu];
 157         other_xc->regs.intRegFile[16] = cpu;
 158         other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu;
 159         other_xc->regs.intRegFile[0] = cpu;
 160         other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
 161         other_xc->setStatus(ExecContext::Active); //Start the cpu
 162         return No_Fault;
 163     }
 164
 165     return No_Fault;
 166 }
 167
 168 void
 169 AlphaConsole::serialize()
 170 {
 171     nameOut();
 172     // assumes full AlphaAccess size
 173     // might have unnecessary fields here
 174     paramOut("last_offset",alphaAccess->last_offset);
 175     paramOut("version",alphaAccess->version);
 176     paramOut("numCPUs",alphaAccess->numCPUs);
 177     paramOut("mem_size",alphaAccess->mem_size);
 178     paramOut("cpuClock",alphaAccess->cpuClock);
 179     paramOut("intrClockFrequency",alphaAccess->intrClockFrequency);
 180     paramOut("kernStart",alphaAccess->kernStart);
 181     paramOut("kernEnd",alphaAccess->kernEnd);
 182     paramOut("entryPoint",alphaAccess->entryPoint);
 183     paramOut("diskUnit",alphaAccess->diskUnit);
 184     paramOut("diskCount",alphaAccess->diskCount);
 185     paramOut("diskPAddr",alphaAccess->diskPAddr);
 186     paramOut("diskBlock",alphaAccess->diskBlock);
 187     paramOut("diskOperation",alphaAccess->diskOperation);
 188     paramOut("outputChar",alphaAccess->outputChar);
 189     paramOut("bootStrapImpure",alphaAccess->bootStrapImpure);
 190     paramOut("bootStrapCPU",alphaAccess->bootStrapCPU);
 191 }
 192
 193 void
 194 AlphaConsole::unserialize(IniFile &db, const std::string &category,
 195                           ConfigNode *node)
 196 {
 197     string data;
 198     db.findDefault(category,"last_offset",data);
 199     to_number(data,alphaAccess->last_offset);
 200     db.findDefault(category,"version",data);
 201     to_number(data,alphaAccess->version);
 202     db.findDefault(category,"numCPUs",data);
 203     to_number(data,alphaAccess->numCPUs);
 204     db.findDefault(category,"mem_size",data);
 205     to_number(data,alphaAccess->mem_size);
 206     db.findDefault(category,"cpuClock",data);
 207     to_number(data,alphaAccess->cpuClock);
 208     db.findDefault(category,"intrClockFrequency",data);
 209     to_number(data,alphaAccess->intrClockFrequency);
 210     db.findDefault(category,"kernStart",data);
 211     to_number(data,alphaAccess->kernStart);
 212     db.findDefault(category,"kernEnd",data);
 213     to_number(data,alphaAccess->kernEnd);
 214     db.findDefault(category,"entryPoint",data);
 215     to_number(data,alphaAccess->entryPoint);
 216     db.findDefault(category,"diskUnit",data);
 217     to_number(data,alphaAccess->diskUnit);
 218     db.findDefault(category,"diskCount",data);
 219     to_number(data,alphaAccess->diskCount);
 220     db.findDefault(category,"diskPAddr",data);
 221     to_number(data,alphaAccess->diskPAddr);
 222     db.findDefault(category,"diskBlock",data);
 223     to_number(data,alphaAccess->diskBlock);
 224     db.findDefault(category,"diskOperation",data);
 225     to_number(data,alphaAccess->diskOperation);
 226     db.findDefault(category,"outputChar",data);
 227     to_number(data,alphaAccess->outputChar);
 228     db.findDefault(category,"bootStrapImpure",data);
 229     to_number(data,alphaAccess->bootStrapImpure);
 230     db.findDefault(category,"bootStrapCPU",data);
 231     to_number(data,alphaAccess->bootStrapCPU);
 232
 233 }
 234
 235 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 236
 237     SimObjectParam<SimConsole *> sim_console;
 238     SimObjectParam<SimpleDisk *> disk;
 239     Param<int> size;
 240     Param<int> num_cpus;
 241     SimObjectParam<MemoryController *> mmu;
 242     Param<Addr> addr;
 243     Param<Addr> mask;
 244     SimObjectParam<System *> system;
 245     SimObjectParam<BaseCPU *> cpu;
 246     SimObjectParam<TlaserClock *> clock;
 247
 248 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 249
 250 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 251
 252     INIT_PARAM(sim_console, "The Simulator Console"),
 253     INIT_PARAM(disk, "Simple Disk"),
 254     INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)),
 255     INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
 256     INIT_PARAM(mmu, "Memory Controller"),
 257     INIT_PARAM(addr, "Device Address"),
 258     INIT_PARAM(mask, "Address Mask"),
 259     INIT_PARAM(system, "system object"),
 260     INIT_PARAM(cpu, "Processor"),
 261     INIT_PARAM(clock, "Turbolaser Clock")
 262
 263 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 264
 265 CREATE_SIM_OBJECT(AlphaConsole)
 266 {
 267     return  new AlphaConsole(getInstanceName(), sim_console,
 268                              disk, size, system,
 269                              cpu, clock, num_cpus,
 270                              addr, mask, mmu);
 271 }
 272
 273 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)