dev/ide_ctrl.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstddef>
  30 #include <cstdlib>
  31 #include <string>
  32 #include <vector>
  33
  34 #include "base/trace.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/dma.hh"
  37 #include "dev/pcireg.h"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/ide_disk.hh"
  40 #include "dev/ide_ctrl.hh"
  41 #include "dev/tsunami_cchip.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/bus/dma_interface.hh"
  46 #include "dev/tsunami.hh"
  47 #include "mem/functional_mem/memory_control.hh"
  48 #include "mem/functional_mem/physical_memory.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/sim_object.hh"
  51
  52 using namespace std;
  53
  54 ////
  55 // Initialization and destruction
  56 ////
  57
  58 IdeController::IdeController(const string &name, IntrControl *ic,
  59                              const vector<IdeDisk *> &new_disks,
  60                              MemoryController *mmu, PciConfigAll *cf,
  61                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
  62                              uint32_t dev_num, uint32_t func_num,
  63                              Bus *host_bus, HierParams *hier)
  64     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
  65 {
  66     // put back pointer into Tsunami
  67     tsunami->disk_controller = this;
  68
  69     // initialize the PIO interface addresses
  70     pri_cmd_addr = 0;
  71     pri_cmd_size = BARSize[0];
  72
  73     pri_ctrl_addr = 0;
  74     pri_ctrl_size = BARSize[1];
  75
  76     sec_cmd_addr = 0;
  77     sec_cmd_size = BARSize[2];
  78
  79     sec_ctrl_addr = 0;
  80     sec_ctrl_size = BARSize[3];
  81
  82     // initialize the bus master interface (BMI) address to be configured
  83     // via PCI
  84     bmi_addr = 0;
  85     bmi_size = BARSize[4];
  86
  87     // zero out all of the registers
  88     memset(bmi_regs, 0, sizeof(bmi_regs));
  89     memset(pci_regs, 0, sizeof(pci_regs));
  90
  91     // setup initial values
  92     *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
  93     *(uint8_t *)&bmi_regs[BMIS0] = 0x60;
  94     *(uint8_t *)&bmi_regs[BMIS1] = 0x60;
  95
  96     // reset all internal variables
  97     io_enabled = false;
  98     bm_enabled = false;
  99     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
 100
 101     // create the PIO and DMA interfaces
 102     if (host_bus) {
 103         pioInterface = newPioInterface(name, hier, host_bus, this,
 104                                        &IdeController::cacheAccess);
 105
 106         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
 107                                              host_bus, 1);
 108     }
 109
 110     // setup the disks attached to controller
 111     memset(disks, 0, sizeof(IdeDisk *) * 4);
 112
 113     if (new_disks.size() > 3)
 114         panic("IDE controllers support a maximum of 4 devices attached!\n");
 115
 116     for (int i = 0; i < new_disks.size(); i++) {
 117         disks[i] = new_disks[i];
 118         disks[i]->setController(this, dmaInterface);
 119     }
 120 }
 121
 122 IdeController::~IdeController()
 123 {
 124     for (int i = 0; i < 4; i++)
 125         if (disks[i])
 126             delete disks[i];
 127 }
 128
 129 ////
 130 // Utility functions
 131 ///
 132
 133 void
 134 IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
 135                          RegType_t &type)
 136 {
 137     offset = addr;
 138
 139     if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
 140         offset -= pri_cmd_addr;
 141         type = COMMAND_BLOCK;
 142         primary = true;
 143     } else if (addr >= pri_ctrl_addr &&
 144                addr < (pri_ctrl_addr + pri_ctrl_size)) {
 145         offset -= pri_ctrl_addr;
 146         type = CONTROL_BLOCK;
 147         primary = true;
 148     } else if (addr >= sec_cmd_addr &&
 149                addr < (sec_cmd_addr + sec_cmd_size)) {
 150         offset -= sec_cmd_addr;
 151         type = COMMAND_BLOCK;
 152         primary = false;
 153     } else if (addr >= sec_ctrl_addr &&
 154                addr < (sec_ctrl_addr + sec_ctrl_size)) {
 155         offset -= sec_ctrl_addr;
 156         type = CONTROL_BLOCK;
 157         primary = false;
 158     } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
 159         offset -= bmi_addr;
 160         type = BMI_BLOCK;
 161         primary = (offset < BMIC1) ? true : false;
 162     } else {
 163         panic("IDE controller access to invalid address: %#x\n", addr);
 164     }
 165 }
 166
 167 int
 168 IdeController::getDisk(bool primary)
 169 {
 170     int disk = 0;
 171     uint8_t *devBit = &dev[0];
 172
 173     if (!primary) {
 174         disk += 2;
 175         devBit = &dev[1];
 176     }
 177
 178     disk += *devBit;
 179
 180     assert(*devBit == 0 || *devBit == 1);
 181
 182     return disk;
 183 }
 184
 185 int
 186 IdeController::getDisk(IdeDisk *diskPtr)
 187 {
 188     for (int i = 0; i < 4; i++) {
 189         if ((long)diskPtr == (long)disks[i])
 190             return i;
 191     }
 192     return -1;
 193 }
 194
 195 ////
 196 // Command completion
 197 ////
 198
 199 void
 200 IdeController::setDmaComplete(IdeDisk *disk)
 201 {
 202     int diskNum = getDisk(disk);
 203
 204     if (diskNum < 0)
 205         panic("Unable to find disk based on pointer %#x\n", disk);
 206
 207     if (diskNum < 2) {
 208         // clear the start/stop bit in the command register
 209         bmi_regs[BMIC0] &= ~SSBM;
 210         // clear the bus master active bit in the status register
 211         bmi_regs[BMIS0] &= ~BMIDEA;
 212         // set the interrupt bit
 213         bmi_regs[BMIS0] |= IDEINTS;
 214     } else {
 215         // clear the start/stop bit in the command register
 216         bmi_regs[BMIC1] &= ~SSBM;
 217         // clear the bus master active bit in the status register
 218         bmi_regs[BMIS1] &= ~BMIDEA;
 219         // set the interrupt bit
 220         bmi_regs[BMIS1] |= IDEINTS;
 221     }
 222 }
 223
 224 ////
 225 // Interrupt handling
 226 ////
 227
 228 void
 229 IdeController::intrPost()
 230 {
 231     tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
 232 }
 233
 234 void
 235 IdeController::intrClear()
 236 {
 237     tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
 238 }
 239
 240 ////
 241 // Bus timing and bus access functions
 242 ////
 243
 244 Tick
 245 IdeController::cacheAccess(MemReqPtr &req)
 246 {
 247     // @todo Add more accurate timing to cache access
 248     return curTick + 1000;
 249 }
 250
 251 ////
 252 // Read and write handling
 253 ////
 254
 255 void
 256 IdeController::ReadConfig(int offset, int size, uint8_t *data)
 257 {
 258
 259 #if TRACING_ON
 260     Addr origOffset = offset;
 261 #endif
 262
 263     if (offset < PCI_DEVICE_SPECIFIC) {
 264         PciDev::ReadConfig(offset, size, data);
 265     } else {
 266         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 267             offset -= PCI_IDE_TIMING;
 268             offset += IDETIM;
 269
 270             if ((offset + size) > (IDETIM + 4))
 271                 panic("PCI read of IDETIM with invalid size\n");
 272         } else if (offset == PCI_SLAVE_TIMING) {
 273             offset -= PCI_SLAVE_TIMING;
 274             offset += SIDETIM;
 275
 276             if ((offset + size) > (SIDETIM + 1))
 277                 panic("PCI read of SIDETIM with invalid size\n");
 278         } else if (offset == PCI_UDMA33_CTRL) {
 279             offset -= PCI_UDMA33_CTRL;
 280             offset += UDMACTL;
 281
 282             if ((offset + size) > (UDMACTL + 1))
 283                 panic("PCI read of UDMACTL with invalid size\n");
 284         } else if (offset >= PCI_UDMA33_TIMING &&
 285                    offset < (PCI_UDMA33_TIMING + 2)) {
 286             offset -= PCI_UDMA33_TIMING;
 287             offset += UDMATIM;
 288
 289             if ((offset + size) > (UDMATIM + 2))
 290                 panic("PCI read of UDMATIM with invalid size\n");
 291         } else {
 292             panic("PCI read of unimplemented register: %x\n", offset);
 293         }
 294
 295         memcpy((void *)data, (void *)&pci_regs[offset], size);
 296     }
 297
 298     DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
 299                 origOffset, offset, size, *(uint32_t *)data);
 300 }
 301
 302 void
 303 IdeController::WriteConfig(int offset, int size, uint32_t data)
 304 {
 305     DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
 306             offset, size, data);
 307
 308     // do standard write stuff if in standard PCI space
 309     if (offset < PCI_DEVICE_SPECIFIC) {
 310         PciDev::WriteConfig(offset, size, data);
 311     } else {
 312         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 313             offset -= PCI_IDE_TIMING;
 314             offset += IDETIM;
 315
 316             if ((offset + size) > (IDETIM + 4))
 317                 panic("PCI write to IDETIM with invalid size\n");
 318         } else if (offset == PCI_SLAVE_TIMING) {
 319             offset -= PCI_SLAVE_TIMING;
 320             offset += SIDETIM;
 321
 322             if ((offset + size) > (SIDETIM + 1))
 323                 panic("PCI write to SIDETIM with invalid size\n");
 324         } else if (offset == PCI_UDMA33_CTRL) {
 325             offset -= PCI_UDMA33_CTRL;
 326             offset += UDMACTL;
 327
 328             if ((offset + size) > (UDMACTL + 1))
 329                 panic("PCI write to UDMACTL with invalid size\n");
 330         } else if (offset >= PCI_UDMA33_TIMING &&
 331                    offset < (PCI_UDMA33_TIMING + 2)) {
 332             offset -= PCI_UDMA33_TIMING;
 333             offset += UDMATIM;
 334
 335             if ((offset + size) > (UDMATIM + 2))
 336                 panic("PCI write to UDMATIM with invalid size\n");
 337         } else {
 338             panic("PCI write to unimplemented register: %x\n", offset);
 339         }
 340
 341         memcpy((void *)&pci_regs[offset], (void *)&data, size);
 342     }
 343
 344     // Catch the writes to specific PCI registers that have side affects
 345     // (like updating the PIO ranges)
 346     switch (offset) {
 347       case PCI_COMMAND:
 348         if (config.data[offset] & PCI_CMD_IOSE)
 349             io_enabled = true;
 350         else
 351             io_enabled = false;
 352
 353         if (config.data[offset] & PCI_CMD_BME)
 354             bm_enabled = true;
 355         else
 356             bm_enabled = false;
 357         break;
 358
 359       case PCI0_BASE_ADDR0:
 360         if (BARAddrs[0] != 0) {
 361             pri_cmd_addr = BARAddrs[0];
 362             if (pioInterface)
 363                 pioInterface->addAddrRange(pri_cmd_addr,
 364                                            pri_cmd_addr + pri_cmd_size - 1);
 365
 366             pri_cmd_addr &= PA_UNCACHED_MASK;
 367         }
 368         break;
 369
 370       case PCI0_BASE_ADDR1:
 371         if (BARAddrs[1] != 0) {
 372             pri_ctrl_addr = BARAddrs[1];
 373             if (pioInterface)
 374                 pioInterface->addAddrRange(pri_ctrl_addr,
 375                                            pri_ctrl_addr + pri_ctrl_size - 1);
 376
 377             pri_ctrl_addr &= PA_UNCACHED_MASK;
 378         }
 379         break;
 380
 381       case PCI0_BASE_ADDR2:
 382         if (BARAddrs[2] != 0) {
 383             sec_cmd_addr = BARAddrs[2];
 384             if (pioInterface)
 385                 pioInterface->addAddrRange(sec_cmd_addr,
 386                                            sec_cmd_addr + sec_cmd_size - 1);
 387
 388             sec_cmd_addr &= PA_UNCACHED_MASK;
 389         }
 390         break;
 391
 392       case PCI0_BASE_ADDR3:
 393         if (BARAddrs[3] != 0) {
 394             sec_ctrl_addr = BARAddrs[3];
 395             if (pioInterface)
 396                 pioInterface->addAddrRange(sec_ctrl_addr,
 397                                            sec_ctrl_addr + sec_ctrl_size - 1);
 398
 399             sec_ctrl_addr &= PA_UNCACHED_MASK;
 400         }
 401         break;
 402
 403       case PCI0_BASE_ADDR4:
 404         if (BARAddrs[4] != 0) {
 405             bmi_addr = BARAddrs[4];
 406             if (pioInterface)
 407                 pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
 408
 409             bmi_addr &= PA_UNCACHED_MASK;
 410         }
 411         break;
 412     }
 413 }
 414
 415 Fault
 416 IdeController::read(MemReqPtr &req, uint8_t *data)
 417 {
 418     Addr offset;
 419     bool primary;
 420     bool byte;
 421     bool cmdBlk;
 422     RegType_t type;
 423     int disk;
 424
 425     parseAddr(req->paddr, offset, primary, type);
 426     byte = (req->size == sizeof(uint8_t)) ? true : false;
 427     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 428
 429     if (!io_enabled)
 430         return No_Fault;
 431
 432     // sanity check the size (allows byte, word, or dword access)
 433     if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
 434         req->size != sizeof(uint32_t))
 435         panic("IDE controller read of invalid size: %#x\n", req->size);
 436
 437     if (type != BMI_BLOCK) {
 438         assert(req->size != sizeof(uint32_t));
 439
 440         disk = getDisk(primary);
 441         if (disks[disk])
 442             disks[disk]->read(offset, byte, cmdBlk, data);
 443     } else {
 444         memcpy((void *)data, &bmi_regs[offset], req->size);
 445     }
 446
 447     DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
 448             offset, req->size, *(uint32_t *)data);
 449
 450     return No_Fault;
 451 }
 452
 453 Fault
 454 IdeController::write(MemReqPtr &req, const uint8_t *data)
 455 {
 456     Addr offset;
 457     bool primary;
 458     bool byte;
 459     bool cmdBlk;
 460     RegType_t type;
 461     int disk;
 462
 463     parseAddr(req->paddr, offset, primary, type);
 464     byte = (req->size == sizeof(uint8_t)) ? true : false;
 465     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 466
 467     DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
 468             offset, req->size, *(uint32_t *)data);
 469
 470     uint8_t oldVal, newVal;
 471
 472     if (!io_enabled)
 473         return No_Fault;
 474
 475     if (type == BMI_BLOCK && !bm_enabled)
 476         return No_Fault;
 477
 478     if (type != BMI_BLOCK) {
 479         // shadow the dev bit
 480         if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
 481             uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
 482             *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
 483         }
 484
 485         assert(req->size != sizeof(uint32_t));
 486
 487         disk = getDisk(primary);
 488         if (disks[disk])
 489             disks[disk]->write(offset, byte, cmdBlk, data);
 490     } else {
 491         switch (offset) {
 492             // Bus master IDE command register
 493           case BMIC1:
 494           case BMIC0:
 495             if (req->size != sizeof(uint8_t))
 496                 panic("Invalid BMIC write size: %x\n", req->size);
 497
 498             // select the current disk based on DEV bit
 499             disk = getDisk(primary);
 500
 501             oldVal = bmi_regs[offset];
 502             newVal = *data;
 503
 504             // if a DMA transfer is in progress, R/W control cannot change
 505             if (oldVal & SSBM) {
 506                 if ((oldVal & RWCON) ^ (newVal & RWCON)) {
 507                     (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
 508                 }
 509             }
 510
 511             // see if the start/stop bit is being changed
 512             if ((oldVal & SSBM) ^ (newVal & SSBM)) {
 513                 if (oldVal & SSBM) {
 514                     // stopping DMA transfer
 515                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 516
 517                     // clear the BMIDEA bit
 518                     bmi_regs[offset + 0x2] &= ~BMIDEA;
 519
 520                     if (disks[disk] == NULL)
 521                         panic("DMA stop for disk %d which does not exist\n",
 522                               disk);
 523
 524                     // inform the disk of the DMA transfer abort
 525                     disks[disk]->abortDma();
 526                 } else {
 527                     // starting DMA transfer
 528                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 529
 530                     // set the BMIDEA bit
 531                     bmi_regs[offset + 0x2] |= BMIDEA;
 532
 533                     if (disks[disk] == NULL)
 534                         panic("DMA start for disk %d which does not exist\n",
 535                               disk);
 536
 537                     // inform the disk of the DMA transfer start
 538                     if (primary)
 539                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
 540                     else
 541                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
 542                 }
 543             }
 544
 545             // update the register value
 546             bmi_regs[offset] = newVal;
 547             break;
 548
 549             // Bus master IDE status register
 550           case BMIS0:
 551           case BMIS1:
 552             if (req->size != sizeof(uint8_t))
 553                 panic("Invalid BMIS write size: %x\n", req->size);
 554
 555             oldVal = bmi_regs[offset];
 556             newVal = *data;
 557
 558             // the BMIDEA bit is RO
 559             newVal |= (oldVal & BMIDEA);
 560
 561             // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
 562             if ((oldVal & IDEINTS) && (newVal & IDEINTS))
 563                 newVal &= ~IDEINTS; // clear the interrupt?
 564             else
 565                 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
 566
 567             if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
 568                 newVal &= ~IDEDMAE;
 569             else
 570                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 571
 572             bmi_regs[offset] = newVal;
 573             break;
 574
 575             // Bus master IDE descriptor table pointer register
 576           case BMIDTP0:
 577           case BMIDTP1:
 578             if (req->size != sizeof(uint32_t))
 579                 panic("Invalid BMIDTP write size: %x\n", req->size);
 580
 581             *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
 582             break;
 583
 584           default:
 585             if (req->size != sizeof(uint8_t) &&
 586                 req->size != sizeof(uint16_t) &&
 587                 req->size != sizeof(uint32_t))
 588                 panic("IDE controller write of invalid write size: %x\n",
 589                       req->size);
 590
 591             // do a default copy of data into the registers
 592             memcpy((void *)&bmi_regs[offset], data, req->size);
 593         }
 594     }
 595
 596     return No_Fault;
 597 }
 598
 599 ////
 600 // Serialization
 601 ////
 602
 603 void
 604 IdeController::serialize(std::ostream &os)
 605 {
 606     // Serialize the PciDev base class
 607     PciDev::serialize(os);
 608
 609     // Serialize register addresses and sizes
 610     SERIALIZE_SCALAR(pri_cmd_addr);
 611     SERIALIZE_SCALAR(pri_cmd_size);
 612     SERIALIZE_SCALAR(pri_ctrl_addr);
 613     SERIALIZE_SCALAR(pri_ctrl_size);
 614     SERIALIZE_SCALAR(sec_cmd_addr);
 615     SERIALIZE_SCALAR(sec_cmd_size);
 616     SERIALIZE_SCALAR(sec_ctrl_addr);
 617     SERIALIZE_SCALAR(sec_ctrl_size);
 618     SERIALIZE_SCALAR(bmi_addr);
 619     SERIALIZE_SCALAR(bmi_size);
 620
 621     // Serialize registers
 622     SERIALIZE_ARRAY(bmi_regs, 16);
 623     SERIALIZE_ARRAY(dev, 2);
 624     SERIALIZE_ARRAY(pci_regs, 8);
 625
 626     // Serialize internal state
 627     SERIALIZE_SCALAR(io_enabled);
 628     SERIALIZE_SCALAR(bm_enabled);
 629     SERIALIZE_ARRAY(cmd_in_progress, 4);
 630 }
 631
 632 void
 633 IdeController::unserialize(Checkpoint *cp, const std::string &section)
 634 {
 635     // Unserialize the PciDev base class
 636     PciDev::unserialize(cp, section);
 637
 638     // Unserialize register addresses and sizes
 639     UNSERIALIZE_SCALAR(pri_cmd_addr);
 640     UNSERIALIZE_SCALAR(pri_cmd_size);
 641     UNSERIALIZE_SCALAR(pri_ctrl_addr);
 642     UNSERIALIZE_SCALAR(pri_ctrl_size);
 643     UNSERIALIZE_SCALAR(sec_cmd_addr);
 644     UNSERIALIZE_SCALAR(sec_cmd_size);
 645     UNSERIALIZE_SCALAR(sec_ctrl_addr);
 646     UNSERIALIZE_SCALAR(sec_ctrl_size);
 647     UNSERIALIZE_SCALAR(bmi_addr);
 648     UNSERIALIZE_SCALAR(bmi_size);
 649
 650     // Unserialize registers
 651     UNSERIALIZE_ARRAY(bmi_regs, 16);
 652     UNSERIALIZE_ARRAY(dev, 2);
 653     UNSERIALIZE_ARRAY(pci_regs, 8);
 654
 655     // Unserialize internal state
 656     UNSERIALIZE_SCALAR(io_enabled);
 657     UNSERIALIZE_SCALAR(bm_enabled);
 658     UNSERIALIZE_ARRAY(cmd_in_progress, 4);
 659
 660     if (pioInterface) {
 661         pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr +
 662                                    pri_cmd_size - 1);
 663         pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr +
 664                                    pri_ctrl_size - 1);
 665         pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr +
 666                                    sec_cmd_size - 1);
 667         pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr +
 668                                    sec_ctrl_size - 1);
 669         pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
 670    }
 671 }
 672
 673 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 674
 675 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 676
 677     SimObjectParam<IntrControl *> intr_ctrl;
 678     SimObjectVectorParam<IdeDisk *> disks;
 679     SimObjectParam<MemoryController *> mmu;
 680     SimObjectParam<PciConfigAll *> configspace;
 681     SimObjectParam<PciConfigData *> configdata;
 682     SimObjectParam<Tsunami *> tsunami;
 683     Param<uint32_t> pci_bus;
 684     Param<uint32_t> pci_dev;
 685     Param<uint32_t> pci_func;
 686     SimObjectParam<Bus *> io_bus;
 687     SimObjectParam<HierParams *> hier;
 688
 689 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 690
 691 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 692
 693     INIT_PARAM(intr_ctrl, "Interrupt Controller"),
 694     INIT_PARAM(disks, "IDE disks attached to this controller"),
 695     INIT_PARAM(mmu, "Memory controller"),
 696     INIT_PARAM(configspace, "PCI Configspace"),
 697     INIT_PARAM(configdata, "PCI Config data"),
 698     INIT_PARAM(tsunami, "Tsunami chipset pointer"),
 699     INIT_PARAM(pci_bus, "PCI bus ID"),
 700     INIT_PARAM(pci_dev, "PCI device number"),
 701     INIT_PARAM(pci_func, "PCI function code"),
 702     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
 703     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 704
 705 END_INIT_SIM_OBJECT_PARAMS(IdeController)
 706
 707 CREATE_SIM_OBJECT(IdeController)
 708 {
 709     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
 710                              configspace, configdata, tsunami, pci_bus,
 711                              pci_dev, pci_func, io_bus, hier);
 712 }
 713
 714 REGISTER_SIM_OBJECT("IdeController", IdeController)
 715
 716 #endif //DOXYGEN_SHOULD_SKIP_THIS