dev/ide_ctrl.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstddef>
  30 #include <cstdlib>
  31 #include <string>
  32 #include <vector>
  33
  34 #include "base/trace.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/dma.hh"
  37 #include "dev/pcireg.h"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/ide_disk.hh"
  40 #include "dev/ide_ctrl.hh"
  41 #include "dev/tsunami_cchip.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/bus/dma_interface.hh"
  46 #include "dev/tsunami.hh"
  47 #include "mem/functional_mem/memory_control.hh"
  48 #include "mem/functional_mem/physical_memory.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/sim_object.hh"
  51
  52 using namespace std;
  53
  54 ////
  55 // Initialization and destruction
  56 ////
  57
  58 IdeController::IdeController(const string &name, IntrControl *ic,
  59                              const vector<IdeDisk *> &new_disks,
  60                              MemoryController *mmu, PciConfigAll *cf,
  61                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
  62                              uint32_t dev_num, uint32_t func_num,
  63                              Bus *host_bus, HierParams *hier)
  64     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
  65 {
  66     // put back pointer into Tsunami
  67     tsunami->disk_controller = this;
  68
  69     // initialize the PIO interface addresses
  70     pri_cmd_addr = 0;
  71     pri_cmd_size = BARSize[0];
  72
  73     pri_ctrl_addr = 0;
  74     pri_ctrl_size = BARSize[1];
  75
  76     sec_cmd_addr = 0;
  77     sec_cmd_size = BARSize[2];
  78
  79     sec_ctrl_addr = 0;
  80     sec_ctrl_size = BARSize[3];
  81
  82     // initialize the bus master interface (BMI) address to be configured
  83     // via PCI
  84     bmi_addr = 0;
  85     bmi_size = BARSize[4];
  86
  87     // zero out all of the registers
  88     memset(bmi_regs, 0, sizeof(bmi_regs));
  89     memset(pci_regs, 0, sizeof(pci_regs));
  90
  91     // setup initial values
  92     *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
  93     *(uint8_t *)&bmi_regs[BMIS0] = 0x60;
  94     *(uint8_t *)&bmi_regs[BMIS1] = 0x60;
  95
  96     // reset all internal variables
  97     io_enabled = false;
  98     bm_enabled = false;
  99     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
 100
 101     // create the PIO and DMA interfaces
 102     if (host_bus) {
 103         pioInterface = newPioInterface(name, hier, host_bus, this,
 104                                        &IdeController::cacheAccess);
 105
 106         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
 107                                              host_bus, 1);
 108     }
 109
 110     // setup the disks attached to controller
 111     memset(disks, 0, sizeof(IdeDisk *) * 4);
 112
 113     if (new_disks.size() > 3)
 114         panic("IDE controllers support a maximum of 4 devices attached!\n");
 115
 116     for (int i = 0; i < new_disks.size(); i++) {
 117         disks[i] = new_disks[i];
 118         disks[i]->setController(this, dmaInterface);
 119     }
 120 }
 121
 122 IdeController::~IdeController()
 123 {
 124     for (int i = 0; i < 4; i++)
 125         if (disks[i])
 126             delete disks[i];
 127 }
 128
 129 ////
 130 // Utility functions
 131 ///
 132
 133 void
 134 IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
 135                          RegType_t &type)
 136 {
 137     offset = addr;
 138
 139     if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
 140         offset -= pri_cmd_addr;
 141         type = COMMAND_BLOCK;
 142         primary = true;
 143     } else if (addr >= pri_ctrl_addr &&
 144                addr < (pri_ctrl_addr + pri_ctrl_size)) {
 145         offset -= pri_ctrl_addr;
 146         type = CONTROL_BLOCK;
 147         primary = true;
 148     } else if (addr >= sec_cmd_addr &&
 149                addr < (sec_cmd_addr + sec_cmd_size)) {
 150         offset -= sec_cmd_addr;
 151         type = COMMAND_BLOCK;
 152         primary = false;
 153     } else if (addr >= sec_ctrl_addr &&
 154                addr < (sec_ctrl_addr + sec_ctrl_size)) {
 155         offset -= sec_ctrl_addr;
 156         type = CONTROL_BLOCK;
 157         primary = false;
 158     } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
 159         offset -= bmi_addr;
 160         type = BMI_BLOCK;
 161         primary = (offset < BMIC1) ? true : false;
 162     } else {
 163         panic("IDE controller access to invalid address: %#x\n", addr);
 164     }
 165 }
 166
 167 int
 168 IdeController::getDisk(bool primary)
 169 {
 170     int disk = 0;
 171     uint8_t *devBit = &dev[0];
 172
 173     if (!primary) {
 174         disk += 2;
 175         devBit = &dev[1];
 176     }
 177
 178     disk += *devBit;
 179
 180     assert(*devBit == 0 || *devBit == 1);
 181
 182     return disk;
 183 }
 184
 185 int
 186 IdeController::getDisk(IdeDisk *diskPtr)
 187 {
 188     for (int i = 0; i < 4; i++) {
 189         if ((long)diskPtr == (long)disks[i])
 190             return i;
 191     }
 192     return -1;
 193 }
 194
 195 bool
 196 IdeController::isDiskSelected(IdeDisk *diskPtr)
 197 {
 198     for (int i = 0; i < 4; i++) {
 199         if ((long)diskPtr == (long)disks[i]) {
 200             // is disk is on primary or secondary channel
 201             int channel = i/2;
 202             // is disk the master or slave
 203             int devID = i%2;
 204
 205             return (dev[channel] == devID);
 206         }
 207     }
 208     panic("Unable to find disk by pointer!!\n");
 209 }
 210
 211 ////
 212 // Command completion
 213 ////
 214
 215 void
 216 IdeController::setDmaComplete(IdeDisk *disk)
 217 {
 218     int diskNum = getDisk(disk);
 219
 220     if (diskNum < 0)
 221         panic("Unable to find disk based on pointer %#x\n", disk);
 222
 223     if (diskNum < 2) {
 224         // clear the start/stop bit in the command register
 225         bmi_regs[BMIC0] &= ~SSBM;
 226         // clear the bus master active bit in the status register
 227         bmi_regs[BMIS0] &= ~BMIDEA;
 228         // set the interrupt bit
 229         bmi_regs[BMIS0] |= IDEINTS;
 230     } else {
 231         // clear the start/stop bit in the command register
 232         bmi_regs[BMIC1] &= ~SSBM;
 233         // clear the bus master active bit in the status register
 234         bmi_regs[BMIS1] &= ~BMIDEA;
 235         // set the interrupt bit
 236         bmi_regs[BMIS1] |= IDEINTS;
 237     }
 238 }
 239
 240 ////
 241 // Interrupt handling
 242 ////
 243
 244 void
 245 IdeController::intrPost()
 246 {
 247     tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
 248 }
 249
 250 void
 251 IdeController::intrClear()
 252 {
 253     tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
 254 }
 255
 256 ////
 257 // Bus timing and bus access functions
 258 ////
 259
 260 Tick
 261 IdeController::cacheAccess(MemReqPtr &req)
 262 {
 263     // @todo Add more accurate timing to cache access
 264     return curTick + 1000;
 265 }
 266
 267 ////
 268 // Read and write handling
 269 ////
 270
 271 void
 272 IdeController::ReadConfig(int offset, int size, uint8_t *data)
 273 {
 274
 275 #if TRACING_ON
 276     Addr origOffset = offset;
 277 #endif
 278
 279     if (offset < PCI_DEVICE_SPECIFIC) {
 280         PciDev::ReadConfig(offset, size, data);
 281     } else {
 282         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 283             offset -= PCI_IDE_TIMING;
 284             offset += IDETIM;
 285
 286             if ((offset + size) > (IDETIM + 4))
 287                 panic("PCI read of IDETIM with invalid size\n");
 288         } else if (offset == PCI_SLAVE_TIMING) {
 289             offset -= PCI_SLAVE_TIMING;
 290             offset += SIDETIM;
 291
 292             if ((offset + size) > (SIDETIM + 1))
 293                 panic("PCI read of SIDETIM with invalid size\n");
 294         } else if (offset == PCI_UDMA33_CTRL) {
 295             offset -= PCI_UDMA33_CTRL;
 296             offset += UDMACTL;
 297
 298             if ((offset + size) > (UDMACTL + 1))
 299                 panic("PCI read of UDMACTL with invalid size\n");
 300         } else if (offset >= PCI_UDMA33_TIMING &&
 301                    offset < (PCI_UDMA33_TIMING + 2)) {
 302             offset -= PCI_UDMA33_TIMING;
 303             offset += UDMATIM;
 304
 305             if ((offset + size) > (UDMATIM + 2))
 306                 panic("PCI read of UDMATIM with invalid size\n");
 307         } else {
 308             panic("PCI read of unimplemented register: %x\n", offset);
 309         }
 310
 311         memcpy((void *)data, (void *)&pci_regs[offset], size);
 312     }
 313
 314     DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
 315                 origOffset, offset, size, *(uint32_t *)data);
 316 }
 317
 318 void
 319 IdeController::WriteConfig(int offset, int size, uint32_t data)
 320 {
 321     DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
 322             offset, size, data);
 323
 324     // do standard write stuff if in standard PCI space
 325     if (offset < PCI_DEVICE_SPECIFIC) {
 326         PciDev::WriteConfig(offset, size, data);
 327     } else {
 328         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 329             offset -= PCI_IDE_TIMING;
 330             offset += IDETIM;
 331
 332             if ((offset + size) > (IDETIM + 4))
 333                 panic("PCI write to IDETIM with invalid size\n");
 334         } else if (offset == PCI_SLAVE_TIMING) {
 335             offset -= PCI_SLAVE_TIMING;
 336             offset += SIDETIM;
 337
 338             if ((offset + size) > (SIDETIM + 1))
 339                 panic("PCI write to SIDETIM with invalid size\n");
 340         } else if (offset == PCI_UDMA33_CTRL) {
 341             offset -= PCI_UDMA33_CTRL;
 342             offset += UDMACTL;
 343
 344             if ((offset + size) > (UDMACTL + 1))
 345                 panic("PCI write to UDMACTL with invalid size\n");
 346         } else if (offset >= PCI_UDMA33_TIMING &&
 347                    offset < (PCI_UDMA33_TIMING + 2)) {
 348             offset -= PCI_UDMA33_TIMING;
 349             offset += UDMATIM;
 350
 351             if ((offset + size) > (UDMATIM + 2))
 352                 panic("PCI write to UDMATIM with invalid size\n");
 353         } else {
 354             panic("PCI write to unimplemented register: %x\n", offset);
 355         }
 356
 357         memcpy((void *)&pci_regs[offset], (void *)&data, size);
 358     }
 359
 360     // Catch the writes to specific PCI registers that have side affects
 361     // (like updating the PIO ranges)
 362     switch (offset) {
 363       case PCI_COMMAND:
 364         if (config.data[offset] & PCI_CMD_IOSE)
 365             io_enabled = true;
 366         else
 367             io_enabled = false;
 368
 369         if (config.data[offset] & PCI_CMD_BME)
 370             bm_enabled = true;
 371         else
 372             bm_enabled = false;
 373         break;
 374
 375       case PCI0_BASE_ADDR0:
 376         if (BARAddrs[0] != 0) {
 377             pri_cmd_addr = BARAddrs[0];
 378             if (pioInterface)
 379                 pioInterface->addAddrRange(pri_cmd_addr,
 380                                            pri_cmd_addr + pri_cmd_size - 1);
 381
 382             pri_cmd_addr &= PA_UNCACHED_MASK;
 383         }
 384         break;
 385
 386       case PCI0_BASE_ADDR1:
 387         if (BARAddrs[1] != 0) {
 388             pri_ctrl_addr = BARAddrs[1];
 389             if (pioInterface)
 390                 pioInterface->addAddrRange(pri_ctrl_addr,
 391                                            pri_ctrl_addr + pri_ctrl_size - 1);
 392
 393             pri_ctrl_addr &= PA_UNCACHED_MASK;
 394         }
 395         break;
 396
 397       case PCI0_BASE_ADDR2:
 398         if (BARAddrs[2] != 0) {
 399             sec_cmd_addr = BARAddrs[2];
 400             if (pioInterface)
 401                 pioInterface->addAddrRange(sec_cmd_addr,
 402                                            sec_cmd_addr + sec_cmd_size - 1);
 403
 404             sec_cmd_addr &= PA_UNCACHED_MASK;
 405         }
 406         break;
 407
 408       case PCI0_BASE_ADDR3:
 409         if (BARAddrs[3] != 0) {
 410             sec_ctrl_addr = BARAddrs[3];
 411             if (pioInterface)
 412                 pioInterface->addAddrRange(sec_ctrl_addr,
 413                                            sec_ctrl_addr + sec_ctrl_size - 1);
 414
 415             sec_ctrl_addr &= PA_UNCACHED_MASK;
 416         }
 417         break;
 418
 419       case PCI0_BASE_ADDR4:
 420         if (BARAddrs[4] != 0) {
 421             bmi_addr = BARAddrs[4];
 422             if (pioInterface)
 423                 pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
 424
 425             bmi_addr &= PA_UNCACHED_MASK;
 426         }
 427         break;
 428     }
 429 }
 430
 431 Fault
 432 IdeController::read(MemReqPtr &req, uint8_t *data)
 433 {
 434     Addr offset;
 435     bool primary;
 436     bool byte;
 437     bool cmdBlk;
 438     RegType_t type;
 439     int disk;
 440
 441     parseAddr(req->paddr, offset, primary, type);
 442     byte = (req->size == sizeof(uint8_t)) ? true : false;
 443     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 444
 445     if (!io_enabled)
 446         return No_Fault;
 447
 448     // sanity check the size (allows byte, word, or dword access)
 449     if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
 450         req->size != sizeof(uint32_t))
 451         panic("IDE controller read of invalid size: %#x\n", req->size);
 452
 453     if (type != BMI_BLOCK) {
 454         assert(req->size != sizeof(uint32_t));
 455
 456         disk = getDisk(primary);
 457         if (disks[disk])
 458             disks[disk]->read(offset, byte, cmdBlk, data);
 459     } else {
 460         memcpy((void *)data, &bmi_regs[offset], req->size);
 461     }
 462
 463     DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
 464             offset, req->size, *(uint32_t *)data);
 465
 466     return No_Fault;
 467 }
 468
 469 Fault
 470 IdeController::write(MemReqPtr &req, const uint8_t *data)
 471 {
 472     Addr offset;
 473     bool primary;
 474     bool byte;
 475     bool cmdBlk;
 476     RegType_t type;
 477     int disk;
 478
 479     parseAddr(req->paddr, offset, primary, type);
 480     byte = (req->size == sizeof(uint8_t)) ? true : false;
 481     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 482
 483     DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
 484             offset, req->size, *(uint32_t *)data);
 485
 486     uint8_t oldVal, newVal;
 487
 488     if (!io_enabled)
 489         return No_Fault;
 490
 491     if (type == BMI_BLOCK && !bm_enabled)
 492         return No_Fault;
 493
 494     if (type != BMI_BLOCK) {
 495         // shadow the dev bit
 496         if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
 497             uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
 498             *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
 499         }
 500
 501         assert(req->size != sizeof(uint32_t));
 502
 503         disk = getDisk(primary);
 504         if (disks[disk])
 505             disks[disk]->write(offset, byte, cmdBlk, data);
 506     } else {
 507         switch (offset) {
 508             // Bus master IDE command register
 509           case BMIC1:
 510           case BMIC0:
 511             if (req->size != sizeof(uint8_t))
 512                 panic("Invalid BMIC write size: %x\n", req->size);
 513
 514             // select the current disk based on DEV bit
 515             disk = getDisk(primary);
 516
 517             oldVal = bmi_regs[offset];
 518             newVal = *data;
 519
 520             // if a DMA transfer is in progress, R/W control cannot change
 521             if (oldVal & SSBM) {
 522                 if ((oldVal & RWCON) ^ (newVal & RWCON)) {
 523                     (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
 524                 }
 525             }
 526
 527             // see if the start/stop bit is being changed
 528             if ((oldVal & SSBM) ^ (newVal & SSBM)) {
 529                 if (oldVal & SSBM) {
 530                     // stopping DMA transfer
 531                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 532
 533                     // clear the BMIDEA bit
 534                     bmi_regs[offset + 0x2] &= ~BMIDEA;
 535
 536                     if (disks[disk] == NULL)
 537                         panic("DMA stop for disk %d which does not exist\n",
 538                               disk);
 539
 540                     // inform the disk of the DMA transfer abort
 541                     disks[disk]->abortDma();
 542                 } else {
 543                     // starting DMA transfer
 544                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 545
 546                     // set the BMIDEA bit
 547                     bmi_regs[offset + 0x2] |= BMIDEA;
 548
 549                     if (disks[disk] == NULL)
 550                         panic("DMA start for disk %d which does not exist\n",
 551                               disk);
 552
 553                     // inform the disk of the DMA transfer start
 554                     if (primary)
 555                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
 556                     else
 557                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
 558                 }
 559             }
 560
 561             // update the register value
 562             bmi_regs[offset] = newVal;
 563             break;
 564
 565             // Bus master IDE status register
 566           case BMIS0:
 567           case BMIS1:
 568             if (req->size != sizeof(uint8_t))
 569                 panic("Invalid BMIS write size: %x\n", req->size);
 570
 571             oldVal = bmi_regs[offset];
 572             newVal = *data;
 573
 574             // the BMIDEA bit is RO
 575             newVal |= (oldVal & BMIDEA);
 576
 577             // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
 578             if ((oldVal & IDEINTS) && (newVal & IDEINTS))
 579                 newVal &= ~IDEINTS; // clear the interrupt?
 580             else
 581                 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
 582
 583             if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
 584                 newVal &= ~IDEDMAE;
 585             else
 586                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 587
 588             bmi_regs[offset] = newVal;
 589             break;
 590
 591             // Bus master IDE descriptor table pointer register
 592           case BMIDTP0:
 593           case BMIDTP1:
 594             if (req->size != sizeof(uint32_t))
 595                 panic("Invalid BMIDTP write size: %x\n", req->size);
 596
 597             *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
 598             break;
 599
 600           default:
 601             if (req->size != sizeof(uint8_t) &&
 602                 req->size != sizeof(uint16_t) &&
 603                 req->size != sizeof(uint32_t))
 604                 panic("IDE controller write of invalid write size: %x\n",
 605                       req->size);
 606
 607             // do a default copy of data into the registers
 608             memcpy((void *)&bmi_regs[offset], data, req->size);
 609         }
 610     }
 611
 612     return No_Fault;
 613 }
 614
 615 ////
 616 // Serialization
 617 ////
 618
 619 void
 620 IdeController::serialize(std::ostream &os)
 621 {
 622     // Serialize the PciDev base class
 623     PciDev::serialize(os);
 624
 625     // Serialize register addresses and sizes
 626     SERIALIZE_SCALAR(pri_cmd_addr);
 627     SERIALIZE_SCALAR(pri_cmd_size);
 628     SERIALIZE_SCALAR(pri_ctrl_addr);
 629     SERIALIZE_SCALAR(pri_ctrl_size);
 630     SERIALIZE_SCALAR(sec_cmd_addr);
 631     SERIALIZE_SCALAR(sec_cmd_size);
 632     SERIALIZE_SCALAR(sec_ctrl_addr);
 633     SERIALIZE_SCALAR(sec_ctrl_size);
 634     SERIALIZE_SCALAR(bmi_addr);
 635     SERIALIZE_SCALAR(bmi_size);
 636
 637     // Serialize registers
 638     SERIALIZE_ARRAY(bmi_regs, 16);
 639     SERIALIZE_ARRAY(dev, 2);
 640     SERIALIZE_ARRAY(pci_regs, 8);
 641
 642     // Serialize internal state
 643     SERIALIZE_SCALAR(io_enabled);
 644     SERIALIZE_SCALAR(bm_enabled);
 645     SERIALIZE_ARRAY(cmd_in_progress, 4);
 646 }
 647
 648 void
 649 IdeController::unserialize(Checkpoint *cp, const std::string &section)
 650 {
 651     // Unserialize the PciDev base class
 652     PciDev::unserialize(cp, section);
 653
 654     // Unserialize register addresses and sizes
 655     UNSERIALIZE_SCALAR(pri_cmd_addr);
 656     UNSERIALIZE_SCALAR(pri_cmd_size);
 657     UNSERIALIZE_SCALAR(pri_ctrl_addr);
 658     UNSERIALIZE_SCALAR(pri_ctrl_size);
 659     UNSERIALIZE_SCALAR(sec_cmd_addr);
 660     UNSERIALIZE_SCALAR(sec_cmd_size);
 661     UNSERIALIZE_SCALAR(sec_ctrl_addr);
 662     UNSERIALIZE_SCALAR(sec_ctrl_size);
 663     UNSERIALIZE_SCALAR(bmi_addr);
 664     UNSERIALIZE_SCALAR(bmi_size);
 665
 666     // Unserialize registers
 667     UNSERIALIZE_ARRAY(bmi_regs, 16);
 668     UNSERIALIZE_ARRAY(dev, 2);
 669     UNSERIALIZE_ARRAY(pci_regs, 8);
 670
 671     // Unserialize internal state
 672     UNSERIALIZE_SCALAR(io_enabled);
 673     UNSERIALIZE_SCALAR(bm_enabled);
 674     UNSERIALIZE_ARRAY(cmd_in_progress, 4);
 675
 676     if (pioInterface) {
 677         pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr +
 678                                    pri_cmd_size - 1);
 679         pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr +
 680                                    pri_ctrl_size - 1);
 681         pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr +
 682                                    sec_cmd_size - 1);
 683         pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr +
 684                                    sec_ctrl_size - 1);
 685         pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
 686    }
 687 }
 688
 689 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 690
 691 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 692
 693     SimObjectParam<IntrControl *> intr_ctrl;
 694     SimObjectVectorParam<IdeDisk *> disks;
 695     SimObjectParam<MemoryController *> mmu;
 696     SimObjectParam<PciConfigAll *> configspace;
 697     SimObjectParam<PciConfigData *> configdata;
 698     SimObjectParam<Tsunami *> tsunami;
 699     Param<uint32_t> pci_bus;
 700     Param<uint32_t> pci_dev;
 701     Param<uint32_t> pci_func;
 702     SimObjectParam<Bus *> io_bus;
 703     SimObjectParam<HierParams *> hier;
 704
 705 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 706
 707 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 708
 709     INIT_PARAM(intr_ctrl, "Interrupt Controller"),
 710     INIT_PARAM(disks, "IDE disks attached to this controller"),
 711     INIT_PARAM(mmu, "Memory controller"),
 712     INIT_PARAM(configspace, "PCI Configspace"),
 713     INIT_PARAM(configdata, "PCI Config data"),
 714     INIT_PARAM(tsunami, "Tsunami chipset pointer"),
 715     INIT_PARAM(pci_bus, "PCI bus ID"),
 716     INIT_PARAM(pci_dev, "PCI device number"),
 717     INIT_PARAM(pci_func, "PCI function code"),
 718     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
 719     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 720
 721 END_INIT_SIM_OBJECT_PARAMS(IdeController)
 722
 723 CREATE_SIM_OBJECT(IdeController)
 724 {
 725     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
 726                              configspace, configdata, tsunami, pci_bus,
 727                              pci_dev, pci_func, io_bus, hier);
 728 }
 729
 730 REGISTER_SIM_OBJECT("IdeController", IdeController)
 731
 732 #endif //DOXYGEN_SHOULD_SKIP_THIS