787049533b577f9da7b2e83d75b268cc7a6785bb
2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "base/trace.hh"
35 #include "cpu/intr_control.hh"
37 #include "dev/pcireg.h"
38 #include "dev/pciconfigall.hh"
39 #include "dev/ide_disk.hh"
40 #include "dev/ide_ctrl.hh"
41 #include "dev/tsunami_cchip.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "mem/bus/dma_interface.hh"
46 #include "dev/tsunami.hh"
47 #include "mem/functional_mem/memory_control.hh"
48 #include "mem/functional_mem/physical_memory.hh"
49 #include "sim/builder.hh"
50 #include "sim/sim_object.hh"
55 // Initialization and destruction
58 IdeController::IdeController(const string
&name
, IntrControl
*ic
,
59 const vector
<IdeDisk
*> &new_disks
,
60 MemoryController
*mmu
, PciConfigAll
*cf
,
61 PciConfigData
*cd
, Tsunami
*t
, uint32_t bus_num
,
62 uint32_t dev_num
, uint32_t func_num
,
63 Bus
*host_bus
, Tick pio_latency
, HierParams
*hier
)
64 : PciDev(name
, mmu
, cf
, cd
, bus_num
, dev_num
, func_num
), tsunami(t
)
66 // initialize the PIO interface addresses
68 pri_cmd_size
= BARSize
[0];
71 pri_ctrl_size
= BARSize
[1];
74 sec_cmd_size
= BARSize
[2];
77 sec_ctrl_size
= BARSize
[3];
79 // initialize the bus master interface (BMI) address to be configured
82 bmi_size
= BARSize
[4];
84 // zero out all of the registers
85 memset(bmi_regs
, 0, sizeof(bmi_regs
));
86 memset(pci_regs
, 0, sizeof(pci_regs
));
88 // setup initial values
89 *(uint32_t *)&pci_regs
[IDETIM
] = 0x80008000; // enable both channels
90 *(uint8_t *)&bmi_regs
[BMIS0
] = 0x60;
91 *(uint8_t *)&bmi_regs
[BMIS1
] = 0x60;
93 // reset all internal variables
96 memset(cmd_in_progress
, 0, sizeof(cmd_in_progress
));
98 // create the PIO and DMA interfaces
100 pioInterface
= newPioInterface(name
, hier
, host_bus
, this,
101 &IdeController::cacheAccess
);
103 dmaInterface
= new DMAInterface
<Bus
>(name
+ ".dma", host_bus
,
105 pioLatency
= pio_latency
* host_bus
->clockRatio
;
108 // setup the disks attached to controller
109 memset(disks
, 0, sizeof(IdeDisk
*) * 4);
111 if (new_disks
.size() > 3)
112 panic("IDE controllers support a maximum of 4 devices attached!\n");
114 for (int i
= 0; i
< new_disks
.size(); i
++) {
115 disks
[i
] = new_disks
[i
];
116 disks
[i
]->setController(this, dmaInterface
);
120 IdeController::~IdeController()
122 for (int i
= 0; i
< 4; i
++)
132 IdeController::parseAddr(const Addr
&addr
, Addr
&offset
, bool &primary
,
137 if (addr
>= pri_cmd_addr
&& addr
< (pri_cmd_addr
+ pri_cmd_size
)) {
138 offset
-= pri_cmd_addr
;
139 type
= COMMAND_BLOCK
;
141 } else if (addr
>= pri_ctrl_addr
&&
142 addr
< (pri_ctrl_addr
+ pri_ctrl_size
)) {
143 offset
-= pri_ctrl_addr
;
144 type
= CONTROL_BLOCK
;
146 } else if (addr
>= sec_cmd_addr
&&
147 addr
< (sec_cmd_addr
+ sec_cmd_size
)) {
148 offset
-= sec_cmd_addr
;
149 type
= COMMAND_BLOCK
;
151 } else if (addr
>= sec_ctrl_addr
&&
152 addr
< (sec_ctrl_addr
+ sec_ctrl_size
)) {
153 offset
-= sec_ctrl_addr
;
154 type
= CONTROL_BLOCK
;
156 } else if (addr
>= bmi_addr
&& addr
< (bmi_addr
+ bmi_size
)) {
159 primary
= (offset
< BMIC1
) ? true : false;
161 panic("IDE controller access to invalid address: %#x\n", addr
);
166 IdeController::getDisk(bool primary
)
169 uint8_t *devBit
= &dev
[0];
178 assert(*devBit
== 0 || *devBit
== 1);
184 IdeController::getDisk(IdeDisk
*diskPtr
)
186 for (int i
= 0; i
< 4; i
++) {
187 if ((long)diskPtr
== (long)disks
[i
])
194 IdeController::isDiskSelected(IdeDisk
*diskPtr
)
196 for (int i
= 0; i
< 4; i
++) {
197 if ((long)diskPtr
== (long)disks
[i
]) {
198 // is disk is on primary or secondary channel
200 // is disk the master or slave
203 return (dev
[channel
] == devID
);
206 panic("Unable to find disk by pointer!!\n");
210 // Command completion
214 IdeController::setDmaComplete(IdeDisk
*disk
)
216 int diskNum
= getDisk(disk
);
219 panic("Unable to find disk based on pointer %#x\n", disk
);
222 // clear the start/stop bit in the command register
223 bmi_regs
[BMIC0
] &= ~SSBM
;
224 // clear the bus master active bit in the status register
225 bmi_regs
[BMIS0
] &= ~BMIDEA
;
226 // set the interrupt bit
227 bmi_regs
[BMIS0
] |= IDEINTS
;
229 // clear the start/stop bit in the command register
230 bmi_regs
[BMIC1
] &= ~SSBM
;
231 // clear the bus master active bit in the status register
232 bmi_regs
[BMIS1
] &= ~BMIDEA
;
233 // set the interrupt bit
234 bmi_regs
[BMIS1
] |= IDEINTS
;
239 // Interrupt handling
243 IdeController::intrPost()
245 tsunami
->cchip
->postDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
249 IdeController::intrClear()
251 tsunami
->cchip
->clearDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
255 // Bus timing and bus access functions
259 IdeController::cacheAccess(MemReqPtr
&req
)
261 // @todo Add more accurate timing to cache access
262 return curTick
+ pioLatency
;
266 // Read and write handling
270 IdeController::ReadConfig(int offset
, int size
, uint8_t *data
)
274 Addr origOffset
= offset
;
277 if (offset
< PCI_DEVICE_SPECIFIC
) {
278 PciDev::ReadConfig(offset
, size
, data
);
280 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
281 offset
-= PCI_IDE_TIMING
;
284 if ((offset
+ size
) > (IDETIM
+ 4))
285 panic("PCI read of IDETIM with invalid size\n");
286 } else if (offset
== PCI_SLAVE_TIMING
) {
287 offset
-= PCI_SLAVE_TIMING
;
290 if ((offset
+ size
) > (SIDETIM
+ 1))
291 panic("PCI read of SIDETIM with invalid size\n");
292 } else if (offset
== PCI_UDMA33_CTRL
) {
293 offset
-= PCI_UDMA33_CTRL
;
296 if ((offset
+ size
) > (UDMACTL
+ 1))
297 panic("PCI read of UDMACTL with invalid size\n");
298 } else if (offset
>= PCI_UDMA33_TIMING
&&
299 offset
< (PCI_UDMA33_TIMING
+ 2)) {
300 offset
-= PCI_UDMA33_TIMING
;
303 if ((offset
+ size
) > (UDMATIM
+ 2))
304 panic("PCI read of UDMATIM with invalid size\n");
306 panic("PCI read of unimplemented register: %x\n", offset
);
309 memcpy((void *)data
, (void *)&pci_regs
[offset
], size
);
312 DPRINTF(IdeCtrl
, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
313 origOffset
, offset
, size
, *(uint32_t *)data
);
317 IdeController::WriteConfig(int offset
, int size
, uint32_t data
)
319 DPRINTF(IdeCtrl
, "IDE PCI write offset: %#x size: %#x data: %#x\n",
322 // do standard write stuff if in standard PCI space
323 if (offset
< PCI_DEVICE_SPECIFIC
) {
324 PciDev::WriteConfig(offset
, size
, data
);
326 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
327 offset
-= PCI_IDE_TIMING
;
330 if ((offset
+ size
) > (IDETIM
+ 4))
331 panic("PCI write to IDETIM with invalid size\n");
332 } else if (offset
== PCI_SLAVE_TIMING
) {
333 offset
-= PCI_SLAVE_TIMING
;
336 if ((offset
+ size
) > (SIDETIM
+ 1))
337 panic("PCI write to SIDETIM with invalid size\n");
338 } else if (offset
== PCI_UDMA33_CTRL
) {
339 offset
-= PCI_UDMA33_CTRL
;
342 if ((offset
+ size
) > (UDMACTL
+ 1))
343 panic("PCI write to UDMACTL with invalid size\n");
344 } else if (offset
>= PCI_UDMA33_TIMING
&&
345 offset
< (PCI_UDMA33_TIMING
+ 2)) {
346 offset
-= PCI_UDMA33_TIMING
;
349 if ((offset
+ size
) > (UDMATIM
+ 2))
350 panic("PCI write to UDMATIM with invalid size\n");
352 panic("PCI write to unimplemented register: %x\n", offset
);
355 memcpy((void *)&pci_regs
[offset
], (void *)&data
, size
);
358 // Catch the writes to specific PCI registers that have side affects
359 // (like updating the PIO ranges)
362 if (config
.data
[offset
] & PCI_CMD_IOSE
)
367 if (config
.data
[offset
] & PCI_CMD_BME
)
373 case PCI0_BASE_ADDR0
:
374 if (BARAddrs
[0] != 0) {
375 pri_cmd_addr
= BARAddrs
[0];
377 pioInterface
->addAddrRange(RangeSize(pri_cmd_addr
,
380 pri_cmd_addr
&= PA_UNCACHED_MASK
;
384 case PCI0_BASE_ADDR1
:
385 if (BARAddrs
[1] != 0) {
386 pri_ctrl_addr
= BARAddrs
[1];
388 pioInterface
->addAddrRange(RangeSize(pri_ctrl_addr
,
391 pri_ctrl_addr
&= PA_UNCACHED_MASK
;
395 case PCI0_BASE_ADDR2
:
396 if (BARAddrs
[2] != 0) {
397 sec_cmd_addr
= BARAddrs
[2];
399 pioInterface
->addAddrRange(RangeSize(sec_cmd_addr
,
402 sec_cmd_addr
&= PA_UNCACHED_MASK
;
406 case PCI0_BASE_ADDR3
:
407 if (BARAddrs
[3] != 0) {
408 sec_ctrl_addr
= BARAddrs
[3];
410 pioInterface
->addAddrRange(RangeSize(sec_ctrl_addr
,
413 sec_ctrl_addr
&= PA_UNCACHED_MASK
;
417 case PCI0_BASE_ADDR4
:
418 if (BARAddrs
[4] != 0) {
419 bmi_addr
= BARAddrs
[4];
421 pioInterface
->addAddrRange(RangeSize(bmi_addr
, bmi_size
));
423 bmi_addr
&= PA_UNCACHED_MASK
;
430 IdeController::read(MemReqPtr
&req
, uint8_t *data
)
439 parseAddr(req
->paddr
, offset
, primary
, type
);
440 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
441 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
446 // sanity check the size (allows byte, word, or dword access)
447 if (req
->size
!= sizeof(uint8_t) && req
->size
!= sizeof(uint16_t) &&
448 req
->size
!= sizeof(uint32_t))
449 panic("IDE controller read of invalid size: %#x\n", req
->size
);
451 if (type
!= BMI_BLOCK
) {
452 assert(req
->size
!= sizeof(uint32_t));
454 disk
= getDisk(primary
);
456 disks
[disk
]->read(offset
, byte
, cmdBlk
, data
);
458 memcpy((void *)data
, &bmi_regs
[offset
], req
->size
);
461 DPRINTF(IdeCtrl
, "IDE read from offset: %#x size: %#x data: %#x\n",
462 offset
, req
->size
, *(uint32_t *)data
);
468 IdeController::write(MemReqPtr
&req
, const uint8_t *data
)
477 parseAddr(req
->paddr
, offset
, primary
, type
);
478 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
479 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
481 DPRINTF(IdeCtrl
, "IDE write from offset: %#x size: %#x data: %#x\n",
482 offset
, req
->size
, *(uint32_t *)data
);
484 uint8_t oldVal
, newVal
;
489 if (type
== BMI_BLOCK
&& !bm_enabled
)
492 if (type
!= BMI_BLOCK
) {
493 // shadow the dev bit
494 if (type
== COMMAND_BLOCK
&& offset
== IDE_SELECT_OFFSET
) {
495 uint8_t *devBit
= (primary
? &dev
[0] : &dev
[1]);
496 *devBit
= ((*data
& IDE_SELECT_DEV_BIT
) ? 1 : 0);
499 assert(req
->size
!= sizeof(uint32_t));
501 disk
= getDisk(primary
);
503 disks
[disk
]->write(offset
, byte
, cmdBlk
, data
);
506 // Bus master IDE command register
509 if (req
->size
!= sizeof(uint8_t))
510 panic("Invalid BMIC write size: %x\n", req
->size
);
512 // select the current disk based on DEV bit
513 disk
= getDisk(primary
);
515 oldVal
= bmi_regs
[offset
];
518 // if a DMA transfer is in progress, R/W control cannot change
520 if ((oldVal
& RWCON
) ^ (newVal
& RWCON
)) {
521 (oldVal
& RWCON
) ? newVal
|= RWCON
: newVal
&= ~RWCON
;
525 // see if the start/stop bit is being changed
526 if ((oldVal
& SSBM
) ^ (newVal
& SSBM
)) {
528 // stopping DMA transfer
529 DPRINTF(IdeCtrl
, "Stopping DMA transfer\n");
531 // clear the BMIDEA bit
532 bmi_regs
[offset
+ 0x2] &= ~BMIDEA
;
534 if (disks
[disk
] == NULL
)
535 panic("DMA stop for disk %d which does not exist\n",
538 // inform the disk of the DMA transfer abort
539 disks
[disk
]->abortDma();
541 // starting DMA transfer
542 DPRINTF(IdeCtrl
, "Starting DMA transfer\n");
544 // set the BMIDEA bit
545 bmi_regs
[offset
+ 0x2] |= BMIDEA
;
547 if (disks
[disk
] == NULL
)
548 panic("DMA start for disk %d which does not exist\n",
551 // inform the disk of the DMA transfer start
553 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP0
]);
555 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP1
]);
559 // update the register value
560 bmi_regs
[offset
] = newVal
;
563 // Bus master IDE status register
566 if (req
->size
!= sizeof(uint8_t))
567 panic("Invalid BMIS write size: %x\n", req
->size
);
569 oldVal
= bmi_regs
[offset
];
572 // the BMIDEA bit is RO
573 newVal
|= (oldVal
& BMIDEA
);
575 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
576 if ((oldVal
& IDEINTS
) && (newVal
& IDEINTS
))
577 newVal
&= ~IDEINTS
; // clear the interrupt?
579 (oldVal
& IDEINTS
) ? newVal
|= IDEINTS
: newVal
&= ~IDEINTS
;
581 if ((oldVal
& IDEDMAE
) && (newVal
& IDEDMAE
))
584 (oldVal
& IDEDMAE
) ? newVal
|= IDEDMAE
: newVal
&= ~IDEDMAE
;
586 bmi_regs
[offset
] = newVal
;
589 // Bus master IDE descriptor table pointer register
592 if (req
->size
!= sizeof(uint32_t))
593 panic("Invalid BMIDTP write size: %x\n", req
->size
);
595 *(uint32_t *)&bmi_regs
[offset
] = *(uint32_t *)data
& ~0x3;
599 if (req
->size
!= sizeof(uint8_t) &&
600 req
->size
!= sizeof(uint16_t) &&
601 req
->size
!= sizeof(uint32_t))
602 panic("IDE controller write of invalid write size: %x\n",
605 // do a default copy of data into the registers
606 memcpy((void *)&bmi_regs
[offset
], data
, req
->size
);
618 IdeController::serialize(std::ostream
&os
)
620 // Serialize the PciDev base class
621 PciDev::serialize(os
);
623 // Serialize register addresses and sizes
624 SERIALIZE_SCALAR(pri_cmd_addr
);
625 SERIALIZE_SCALAR(pri_cmd_size
);
626 SERIALIZE_SCALAR(pri_ctrl_addr
);
627 SERIALIZE_SCALAR(pri_ctrl_size
);
628 SERIALIZE_SCALAR(sec_cmd_addr
);
629 SERIALIZE_SCALAR(sec_cmd_size
);
630 SERIALIZE_SCALAR(sec_ctrl_addr
);
631 SERIALIZE_SCALAR(sec_ctrl_size
);
632 SERIALIZE_SCALAR(bmi_addr
);
633 SERIALIZE_SCALAR(bmi_size
);
635 // Serialize registers
636 SERIALIZE_ARRAY(bmi_regs
, 16);
637 SERIALIZE_ARRAY(dev
, 2);
638 SERIALIZE_ARRAY(pci_regs
, 8);
640 // Serialize internal state
641 SERIALIZE_SCALAR(io_enabled
);
642 SERIALIZE_SCALAR(bm_enabled
);
643 SERIALIZE_ARRAY(cmd_in_progress
, 4);
647 IdeController::unserialize(Checkpoint
*cp
, const std::string
§ion
)
649 // Unserialize the PciDev base class
650 PciDev::unserialize(cp
, section
);
652 // Unserialize register addresses and sizes
653 UNSERIALIZE_SCALAR(pri_cmd_addr
);
654 UNSERIALIZE_SCALAR(pri_cmd_size
);
655 UNSERIALIZE_SCALAR(pri_ctrl_addr
);
656 UNSERIALIZE_SCALAR(pri_ctrl_size
);
657 UNSERIALIZE_SCALAR(sec_cmd_addr
);
658 UNSERIALIZE_SCALAR(sec_cmd_size
);
659 UNSERIALIZE_SCALAR(sec_ctrl_addr
);
660 UNSERIALIZE_SCALAR(sec_ctrl_size
);
661 UNSERIALIZE_SCALAR(bmi_addr
);
662 UNSERIALIZE_SCALAR(bmi_size
);
664 // Unserialize registers
665 UNSERIALIZE_ARRAY(bmi_regs
, 16);
666 UNSERIALIZE_ARRAY(dev
, 2);
667 UNSERIALIZE_ARRAY(pci_regs
, 8);
669 // Unserialize internal state
670 UNSERIALIZE_SCALAR(io_enabled
);
671 UNSERIALIZE_SCALAR(bm_enabled
);
672 UNSERIALIZE_ARRAY(cmd_in_progress
, 4);
675 pioInterface
->addAddrRange(RangeSize(pri_cmd_addr
, pri_cmd_size
));
676 pioInterface
->addAddrRange(RangeSize(pri_ctrl_addr
, pri_ctrl_size
));
677 pioInterface
->addAddrRange(RangeSize(sec_cmd_addr
, sec_cmd_size
));
678 pioInterface
->addAddrRange(RangeSize(sec_ctrl_addr
, sec_ctrl_size
));
679 pioInterface
->addAddrRange(RangeSize(bmi_addr
, bmi_size
));
683 #ifndef DOXYGEN_SHOULD_SKIP_THIS
685 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
687 SimObjectParam
<IntrControl
*> intr_ctrl
;
688 SimObjectVectorParam
<IdeDisk
*> disks
;
689 SimObjectParam
<MemoryController
*> mmu
;
690 SimObjectParam
<PciConfigAll
*> configspace
;
691 SimObjectParam
<PciConfigData
*> configdata
;
692 SimObjectParam
<Tsunami
*> tsunami
;
693 Param
<uint32_t> pci_bus
;
694 Param
<uint32_t> pci_dev
;
695 Param
<uint32_t> pci_func
;
696 SimObjectParam
<Bus
*> io_bus
;
697 Param
<Tick
> pio_latency
;
698 SimObjectParam
<HierParams
*> hier
;
700 END_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
702 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController
)
704 INIT_PARAM(intr_ctrl
, "Interrupt Controller"),
705 INIT_PARAM(disks
, "IDE disks attached to this controller"),
706 INIT_PARAM(mmu
, "Memory controller"),
707 INIT_PARAM(configspace
, "PCI Configspace"),
708 INIT_PARAM(configdata
, "PCI Config data"),
709 INIT_PARAM(tsunami
, "Tsunami chipset pointer"),
710 INIT_PARAM(pci_bus
, "PCI bus ID"),
711 INIT_PARAM(pci_dev
, "PCI device number"),
712 INIT_PARAM(pci_func
, "PCI function code"),
713 INIT_PARAM_DFLT(io_bus
, "Host bus to attach to", NULL
),
714 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
715 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
717 END_INIT_SIM_OBJECT_PARAMS(IdeController
)
719 CREATE_SIM_OBJECT(IdeController
)
721 return new IdeController(getInstanceName(), intr_ctrl
, disks
, mmu
,
722 configspace
, configdata
, tsunami
, pci_bus
,
723 pci_dev
, pci_func
, io_bus
, pio_latency
, hier
);
726 REGISTER_SIM_OBJECT("IdeController", IdeController
)
728 #endif //DOXYGEN_SHOULD_SKIP_THIS