dev/ide_ctrl.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstddef>
  30 #include <cstdlib>
  31 #include <string>
  32 #include <vector>
  33
  34 #include "base/trace.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/dma.hh"
  37 #include "dev/pcireg.h"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/ide_disk.hh"
  40 #include "dev/ide_ctrl.hh"
  41 #include "dev/tsunami_cchip.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/bus/dma_interface.hh"
  46 #include "dev/tsunami.hh"
  47 #include "mem/functional_mem/memory_control.hh"
  48 #include "mem/functional_mem/physical_memory.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/sim_object.hh"
  51
  52 using namespace std;
  53
  54 ////
  55 // Initialization and destruction
  56 ////
  57
  58 IdeController::IdeController(const string &name, IntrControl *ic,
  59                              const vector<IdeDisk *> &new_disks,
  60                              MemoryController *mmu, PciConfigAll *cf,
  61                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
  62                              uint32_t dev_num, uint32_t func_num,
  63                              Bus *host_bus, Tick pio_latency, HierParams *hier)
  64     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
  65 {
  66     // initialize the PIO interface addresses
  67     pri_cmd_addr = 0;
  68     pri_cmd_size = BARSize[0];
  69
  70     pri_ctrl_addr = 0;
  71     pri_ctrl_size = BARSize[1];
  72
  73     sec_cmd_addr = 0;
  74     sec_cmd_size = BARSize[2];
  75
  76     sec_ctrl_addr = 0;
  77     sec_ctrl_size = BARSize[3];
  78
  79     // initialize the bus master interface (BMI) address to be configured
  80     // via PCI
  81     bmi_addr = 0;
  82     bmi_size = BARSize[4];
  83
  84     // zero out all of the registers
  85     memset(bmi_regs, 0, sizeof(bmi_regs));
  86     memset(pci_regs, 0, sizeof(pci_regs));
  87
  88     // setup initial values
  89     *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
  90     *(uint8_t *)&bmi_regs[BMIS0] = 0x60;
  91     *(uint8_t *)&bmi_regs[BMIS1] = 0x60;
  92
  93     // reset all internal variables
  94     io_enabled = false;
  95     bm_enabled = false;
  96     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
  97
  98     // create the PIO and DMA interfaces
  99     if (host_bus) {
 100         pioInterface = newPioInterface(name, hier, host_bus, this,
 101                                        &IdeController::cacheAccess);
 102
 103         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
 104                                              host_bus, 1);
 105         pioLatency = pio_latency * host_bus->clockRatio;
 106     }
 107
 108     // setup the disks attached to controller
 109     memset(disks, 0, sizeof(IdeDisk *) * 4);
 110
 111     if (new_disks.size() > 3)
 112         panic("IDE controllers support a maximum of 4 devices attached!\n");
 113
 114     for (int i = 0; i < new_disks.size(); i++) {
 115         disks[i] = new_disks[i];
 116         disks[i]->setController(this, dmaInterface);
 117     }
 118 }
 119
 120 IdeController::~IdeController()
 121 {
 122     for (int i = 0; i < 4; i++)
 123         if (disks[i])
 124             delete disks[i];
 125 }
 126
 127 ////
 128 // Utility functions
 129 ///
 130
 131 void
 132 IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
 133                          RegType_t &type)
 134 {
 135     offset = addr;
 136
 137     if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
 138         offset -= pri_cmd_addr;
 139         type = COMMAND_BLOCK;
 140         primary = true;
 141     } else if (addr >= pri_ctrl_addr &&
 142                addr < (pri_ctrl_addr + pri_ctrl_size)) {
 143         offset -= pri_ctrl_addr;
 144         type = CONTROL_BLOCK;
 145         primary = true;
 146     } else if (addr >= sec_cmd_addr &&
 147                addr < (sec_cmd_addr + sec_cmd_size)) {
 148         offset -= sec_cmd_addr;
 149         type = COMMAND_BLOCK;
 150         primary = false;
 151     } else if (addr >= sec_ctrl_addr &&
 152                addr < (sec_ctrl_addr + sec_ctrl_size)) {
 153         offset -= sec_ctrl_addr;
 154         type = CONTROL_BLOCK;
 155         primary = false;
 156     } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
 157         offset -= bmi_addr;
 158         type = BMI_BLOCK;
 159         primary = (offset < BMIC1) ? true : false;
 160     } else {
 161         panic("IDE controller access to invalid address: %#x\n", addr);
 162     }
 163 }
 164
 165 int
 166 IdeController::getDisk(bool primary)
 167 {
 168     int disk = 0;
 169     uint8_t *devBit = &dev[0];
 170
 171     if (!primary) {
 172         disk += 2;
 173         devBit = &dev[1];
 174     }
 175
 176     disk += *devBit;
 177
 178     assert(*devBit == 0 || *devBit == 1);
 179
 180     return disk;
 181 }
 182
 183 int
 184 IdeController::getDisk(IdeDisk *diskPtr)
 185 {
 186     for (int i = 0; i < 4; i++) {
 187         if ((long)diskPtr == (long)disks[i])
 188             return i;
 189     }
 190     return -1;
 191 }
 192
 193 bool
 194 IdeController::isDiskSelected(IdeDisk *diskPtr)
 195 {
 196     for (int i = 0; i < 4; i++) {
 197         if ((long)diskPtr == (long)disks[i]) {
 198             // is disk is on primary or secondary channel
 199             int channel = i/2;
 200             // is disk the master or slave
 201             int devID = i%2;
 202
 203             return (dev[channel] == devID);
 204         }
 205     }
 206     panic("Unable to find disk by pointer!!\n");
 207 }
 208
 209 ////
 210 // Command completion
 211 ////
 212
 213 void
 214 IdeController::setDmaComplete(IdeDisk *disk)
 215 {
 216     int diskNum = getDisk(disk);
 217
 218     if (diskNum < 0)
 219         panic("Unable to find disk based on pointer %#x\n", disk);
 220
 221     if (diskNum < 2) {
 222         // clear the start/stop bit in the command register
 223         bmi_regs[BMIC0] &= ~SSBM;
 224         // clear the bus master active bit in the status register
 225         bmi_regs[BMIS0] &= ~BMIDEA;
 226         // set the interrupt bit
 227         bmi_regs[BMIS0] |= IDEINTS;
 228     } else {
 229         // clear the start/stop bit in the command register
 230         bmi_regs[BMIC1] &= ~SSBM;
 231         // clear the bus master active bit in the status register
 232         bmi_regs[BMIS1] &= ~BMIDEA;
 233         // set the interrupt bit
 234         bmi_regs[BMIS1] |= IDEINTS;
 235     }
 236 }
 237
 238 ////
 239 // Interrupt handling
 240 ////
 241
 242 void
 243 IdeController::intrPost()
 244 {
 245     tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
 246 }
 247
 248 void
 249 IdeController::intrClear()
 250 {
 251     tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
 252 }
 253
 254 ////
 255 // Bus timing and bus access functions
 256 ////
 257
 258 Tick
 259 IdeController::cacheAccess(MemReqPtr &req)
 260 {
 261     // @todo Add more accurate timing to cache access
 262     return curTick + pioLatency;
 263 }
 264
 265 ////
 266 // Read and write handling
 267 ////
 268
 269 void
 270 IdeController::ReadConfig(int offset, int size, uint8_t *data)
 271 {
 272
 273 #if TRACING_ON
 274     Addr origOffset = offset;
 275 #endif
 276
 277     if (offset < PCI_DEVICE_SPECIFIC) {
 278         PciDev::ReadConfig(offset, size, data);
 279     } else {
 280         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 281             offset -= PCI_IDE_TIMING;
 282             offset += IDETIM;
 283
 284             if ((offset + size) > (IDETIM + 4))
 285                 panic("PCI read of IDETIM with invalid size\n");
 286         } else if (offset == PCI_SLAVE_TIMING) {
 287             offset -= PCI_SLAVE_TIMING;
 288             offset += SIDETIM;
 289
 290             if ((offset + size) > (SIDETIM + 1))
 291                 panic("PCI read of SIDETIM with invalid size\n");
 292         } else if (offset == PCI_UDMA33_CTRL) {
 293             offset -= PCI_UDMA33_CTRL;
 294             offset += UDMACTL;
 295
 296             if ((offset + size) > (UDMACTL + 1))
 297                 panic("PCI read of UDMACTL with invalid size\n");
 298         } else if (offset >= PCI_UDMA33_TIMING &&
 299                    offset < (PCI_UDMA33_TIMING + 2)) {
 300             offset -= PCI_UDMA33_TIMING;
 301             offset += UDMATIM;
 302
 303             if ((offset + size) > (UDMATIM + 2))
 304                 panic("PCI read of UDMATIM with invalid size\n");
 305         } else {
 306             panic("PCI read of unimplemented register: %x\n", offset);
 307         }
 308
 309         memcpy((void *)data, (void *)&pci_regs[offset], size);
 310     }
 311
 312     DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
 313                 origOffset, offset, size, *(uint32_t *)data);
 314 }
 315
 316 void
 317 IdeController::WriteConfig(int offset, int size, uint32_t data)
 318 {
 319     DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
 320             offset, size, data);
 321
 322     // do standard write stuff if in standard PCI space
 323     if (offset < PCI_DEVICE_SPECIFIC) {
 324         PciDev::WriteConfig(offset, size, data);
 325     } else {
 326         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 327             offset -= PCI_IDE_TIMING;
 328             offset += IDETIM;
 329
 330             if ((offset + size) > (IDETIM + 4))
 331                 panic("PCI write to IDETIM with invalid size\n");
 332         } else if (offset == PCI_SLAVE_TIMING) {
 333             offset -= PCI_SLAVE_TIMING;
 334             offset += SIDETIM;
 335
 336             if ((offset + size) > (SIDETIM + 1))
 337                 panic("PCI write to SIDETIM with invalid size\n");
 338         } else if (offset == PCI_UDMA33_CTRL) {
 339             offset -= PCI_UDMA33_CTRL;
 340             offset += UDMACTL;
 341
 342             if ((offset + size) > (UDMACTL + 1))
 343                 panic("PCI write to UDMACTL with invalid size\n");
 344         } else if (offset >= PCI_UDMA33_TIMING &&
 345                    offset < (PCI_UDMA33_TIMING + 2)) {
 346             offset -= PCI_UDMA33_TIMING;
 347             offset += UDMATIM;
 348
 349             if ((offset + size) > (UDMATIM + 2))
 350                 panic("PCI write to UDMATIM with invalid size\n");
 351         } else {
 352             panic("PCI write to unimplemented register: %x\n", offset);
 353         }
 354
 355         memcpy((void *)&pci_regs[offset], (void *)&data, size);
 356     }
 357
 358     // Catch the writes to specific PCI registers that have side affects
 359     // (like updating the PIO ranges)
 360     switch (offset) {
 361       case PCI_COMMAND:
 362         if (config.data[offset] & PCI_CMD_IOSE)
 363             io_enabled = true;
 364         else
 365             io_enabled = false;
 366
 367         if (config.data[offset] & PCI_CMD_BME)
 368             bm_enabled = true;
 369         else
 370             bm_enabled = false;
 371         break;
 372
 373       case PCI0_BASE_ADDR0:
 374         if (BARAddrs[0] != 0) {
 375             pri_cmd_addr = BARAddrs[0];
 376             if (pioInterface)
 377                 pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
 378                                                      pri_cmd_size));
 379
 380             pri_cmd_addr &= PA_UNCACHED_MASK;
 381         }
 382         break;
 383
 384       case PCI0_BASE_ADDR1:
 385         if (BARAddrs[1] != 0) {
 386             pri_ctrl_addr = BARAddrs[1];
 387             if (pioInterface)
 388                 pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
 389                                                      pri_ctrl_size));
 390
 391             pri_ctrl_addr &= PA_UNCACHED_MASK;
 392         }
 393         break;
 394
 395       case PCI0_BASE_ADDR2:
 396         if (BARAddrs[2] != 0) {
 397             sec_cmd_addr = BARAddrs[2];
 398             if (pioInterface)
 399                 pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
 400                                                      sec_cmd_size));
 401
 402             sec_cmd_addr &= PA_UNCACHED_MASK;
 403         }
 404         break;
 405
 406       case PCI0_BASE_ADDR3:
 407         if (BARAddrs[3] != 0) {
 408             sec_ctrl_addr = BARAddrs[3];
 409             if (pioInterface)
 410                 pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
 411                                                      sec_ctrl_size));
 412
 413             sec_ctrl_addr &= PA_UNCACHED_MASK;
 414         }
 415         break;
 416
 417       case PCI0_BASE_ADDR4:
 418         if (BARAddrs[4] != 0) {
 419             bmi_addr = BARAddrs[4];
 420             if (pioInterface)
 421                 pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
 422
 423             bmi_addr &= PA_UNCACHED_MASK;
 424         }
 425         break;
 426     }
 427 }
 428
 429 Fault
 430 IdeController::read(MemReqPtr &req, uint8_t *data)
 431 {
 432     Addr offset;
 433     bool primary;
 434     bool byte;
 435     bool cmdBlk;
 436     RegType_t type;
 437     int disk;
 438
 439     parseAddr(req->paddr, offset, primary, type);
 440     byte = (req->size == sizeof(uint8_t)) ? true : false;
 441     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 442
 443     if (!io_enabled)
 444         return No_Fault;
 445
 446     // sanity check the size (allows byte, word, or dword access)
 447     if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
 448         req->size != sizeof(uint32_t))
 449         panic("IDE controller read of invalid size: %#x\n", req->size);
 450
 451     if (type != BMI_BLOCK) {
 452         assert(req->size != sizeof(uint32_t));
 453
 454         disk = getDisk(primary);
 455         if (disks[disk])
 456             disks[disk]->read(offset, byte, cmdBlk, data);
 457     } else {
 458         memcpy((void *)data, &bmi_regs[offset], req->size);
 459     }
 460
 461     DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
 462             offset, req->size, *(uint32_t *)data);
 463
 464     return No_Fault;
 465 }
 466
 467 Fault
 468 IdeController::write(MemReqPtr &req, const uint8_t *data)
 469 {
 470     Addr offset;
 471     bool primary;
 472     bool byte;
 473     bool cmdBlk;
 474     RegType_t type;
 475     int disk;
 476
 477     parseAddr(req->paddr, offset, primary, type);
 478     byte = (req->size == sizeof(uint8_t)) ? true : false;
 479     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 480
 481     DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
 482             offset, req->size, *(uint32_t *)data);
 483
 484     uint8_t oldVal, newVal;
 485
 486     if (!io_enabled)
 487         return No_Fault;
 488
 489     if (type == BMI_BLOCK && !bm_enabled)
 490         return No_Fault;
 491
 492     if (type != BMI_BLOCK) {
 493         // shadow the dev bit
 494         if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
 495             uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
 496             *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
 497         }
 498
 499         assert(req->size != sizeof(uint32_t));
 500
 501         disk = getDisk(primary);
 502         if (disks[disk])
 503             disks[disk]->write(offset, byte, cmdBlk, data);
 504     } else {
 505         switch (offset) {
 506             // Bus master IDE command register
 507           case BMIC1:
 508           case BMIC0:
 509             if (req->size != sizeof(uint8_t))
 510                 panic("Invalid BMIC write size: %x\n", req->size);
 511
 512             // select the current disk based on DEV bit
 513             disk = getDisk(primary);
 514
 515             oldVal = bmi_regs[offset];
 516             newVal = *data;
 517
 518             // if a DMA transfer is in progress, R/W control cannot change
 519             if (oldVal & SSBM) {
 520                 if ((oldVal & RWCON) ^ (newVal & RWCON)) {
 521                     (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
 522                 }
 523             }
 524
 525             // see if the start/stop bit is being changed
 526             if ((oldVal & SSBM) ^ (newVal & SSBM)) {
 527                 if (oldVal & SSBM) {
 528                     // stopping DMA transfer
 529                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 530
 531                     // clear the BMIDEA bit
 532                     bmi_regs[offset + 0x2] &= ~BMIDEA;
 533
 534                     if (disks[disk] == NULL)
 535                         panic("DMA stop for disk %d which does not exist\n",
 536                               disk);
 537
 538                     // inform the disk of the DMA transfer abort
 539                     disks[disk]->abortDma();
 540                 } else {
 541                     // starting DMA transfer
 542                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 543
 544                     // set the BMIDEA bit
 545                     bmi_regs[offset + 0x2] |= BMIDEA;
 546
 547                     if (disks[disk] == NULL)
 548                         panic("DMA start for disk %d which does not exist\n",
 549                               disk);
 550
 551                     // inform the disk of the DMA transfer start
 552                     if (primary)
 553                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
 554                     else
 555                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
 556                 }
 557             }
 558
 559             // update the register value
 560             bmi_regs[offset] = newVal;
 561             break;
 562
 563             // Bus master IDE status register
 564           case BMIS0:
 565           case BMIS1:
 566             if (req->size != sizeof(uint8_t))
 567                 panic("Invalid BMIS write size: %x\n", req->size);
 568
 569             oldVal = bmi_regs[offset];
 570             newVal = *data;
 571
 572             // the BMIDEA bit is RO
 573             newVal |= (oldVal & BMIDEA);
 574
 575             // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
 576             if ((oldVal & IDEINTS) && (newVal & IDEINTS))
 577                 newVal &= ~IDEINTS; // clear the interrupt?
 578             else
 579                 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
 580
 581             if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
 582                 newVal &= ~IDEDMAE;
 583             else
 584                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 585
 586             bmi_regs[offset] = newVal;
 587             break;
 588
 589             // Bus master IDE descriptor table pointer register
 590           case BMIDTP0:
 591           case BMIDTP1:
 592             if (req->size != sizeof(uint32_t))
 593                 panic("Invalid BMIDTP write size: %x\n", req->size);
 594
 595             *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
 596             break;
 597
 598           default:
 599             if (req->size != sizeof(uint8_t) &&
 600                 req->size != sizeof(uint16_t) &&
 601                 req->size != sizeof(uint32_t))
 602                 panic("IDE controller write of invalid write size: %x\n",
 603                       req->size);
 604
 605             // do a default copy of data into the registers
 606             memcpy((void *)&bmi_regs[offset], data, req->size);
 607         }
 608     }
 609
 610     return No_Fault;
 611 }
 612
 613 ////
 614 // Serialization
 615 ////
 616
 617 void
 618 IdeController::serialize(std::ostream &os)
 619 {
 620     // Serialize the PciDev base class
 621     PciDev::serialize(os);
 622
 623     // Serialize register addresses and sizes
 624     SERIALIZE_SCALAR(pri_cmd_addr);
 625     SERIALIZE_SCALAR(pri_cmd_size);
 626     SERIALIZE_SCALAR(pri_ctrl_addr);
 627     SERIALIZE_SCALAR(pri_ctrl_size);
 628     SERIALIZE_SCALAR(sec_cmd_addr);
 629     SERIALIZE_SCALAR(sec_cmd_size);
 630     SERIALIZE_SCALAR(sec_ctrl_addr);
 631     SERIALIZE_SCALAR(sec_ctrl_size);
 632     SERIALIZE_SCALAR(bmi_addr);
 633     SERIALIZE_SCALAR(bmi_size);
 634
 635     // Serialize registers
 636     SERIALIZE_ARRAY(bmi_regs, 16);
 637     SERIALIZE_ARRAY(dev, 2);
 638     SERIALIZE_ARRAY(pci_regs, 8);
 639
 640     // Serialize internal state
 641     SERIALIZE_SCALAR(io_enabled);
 642     SERIALIZE_SCALAR(bm_enabled);
 643     SERIALIZE_ARRAY(cmd_in_progress, 4);
 644 }
 645
 646 void
 647 IdeController::unserialize(Checkpoint *cp, const std::string &section)
 648 {
 649     // Unserialize the PciDev base class
 650     PciDev::unserialize(cp, section);
 651
 652     // Unserialize register addresses and sizes
 653     UNSERIALIZE_SCALAR(pri_cmd_addr);
 654     UNSERIALIZE_SCALAR(pri_cmd_size);
 655     UNSERIALIZE_SCALAR(pri_ctrl_addr);
 656     UNSERIALIZE_SCALAR(pri_ctrl_size);
 657     UNSERIALIZE_SCALAR(sec_cmd_addr);
 658     UNSERIALIZE_SCALAR(sec_cmd_size);
 659     UNSERIALIZE_SCALAR(sec_ctrl_addr);
 660     UNSERIALIZE_SCALAR(sec_ctrl_size);
 661     UNSERIALIZE_SCALAR(bmi_addr);
 662     UNSERIALIZE_SCALAR(bmi_size);
 663
 664     // Unserialize registers
 665     UNSERIALIZE_ARRAY(bmi_regs, 16);
 666     UNSERIALIZE_ARRAY(dev, 2);
 667     UNSERIALIZE_ARRAY(pci_regs, 8);
 668
 669     // Unserialize internal state
 670     UNSERIALIZE_SCALAR(io_enabled);
 671     UNSERIALIZE_SCALAR(bm_enabled);
 672     UNSERIALIZE_ARRAY(cmd_in_progress, 4);
 673
 674     if (pioInterface) {
 675         pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
 676         pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
 677         pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
 678         pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
 679         pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
 680    }
 681 }
 682
 683 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 684
 685 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 686
 687     SimObjectParam<IntrControl *> intr_ctrl;
 688     SimObjectVectorParam<IdeDisk *> disks;
 689     SimObjectParam<MemoryController *> mmu;
 690     SimObjectParam<PciConfigAll *> configspace;
 691     SimObjectParam<PciConfigData *> configdata;
 692     SimObjectParam<Tsunami *> tsunami;
 693     Param<uint32_t> pci_bus;
 694     Param<uint32_t> pci_dev;
 695     Param<uint32_t> pci_func;
 696     SimObjectParam<Bus *> io_bus;
 697     Param<Tick> pio_latency;
 698     SimObjectParam<HierParams *> hier;
 699
 700 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 701
 702 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 703
 704     INIT_PARAM(intr_ctrl, "Interrupt Controller"),
 705     INIT_PARAM(disks, "IDE disks attached to this controller"),
 706     INIT_PARAM(mmu, "Memory controller"),
 707     INIT_PARAM(configspace, "PCI Configspace"),
 708     INIT_PARAM(configdata, "PCI Config data"),
 709     INIT_PARAM(tsunami, "Tsunami chipset pointer"),
 710     INIT_PARAM(pci_bus, "PCI bus ID"),
 711     INIT_PARAM(pci_dev, "PCI device number"),
 712     INIT_PARAM(pci_func, "PCI function code"),
 713     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
 714     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 715     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 716
 717 END_INIT_SIM_OBJECT_PARAMS(IdeController)
 718
 719 CREATE_SIM_OBJECT(IdeController)
 720 {
 721     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
 722                              configspace, configdata, tsunami, pci_bus,
 723                              pci_dev, pci_func, io_bus, pio_latency, hier);
 724 }
 725
 726 REGISTER_SIM_OBJECT("IdeController", IdeController)
 727
 728 #endif //DOXYGEN_SHOULD_SKIP_THIS