2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "base/trace.hh"
35 #include "cpu/intr_control.hh"
37 #include "dev/ide_ctrl.hh"
38 #include "dev/ide_disk.hh"
39 #include "dev/pciconfigall.hh"
40 #include "dev/pcireg.h"
41 #include "dev/platform.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/dma_interface.hh"
44 #include "mem/bus/pio_interface.hh"
45 #include "mem/bus/pio_interface_impl.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "mem/functional_mem/physical_memory.hh"
48 #include "sim/builder.hh"
49 #include "sim/sim_object.hh"
54 // Initialization and destruction
57 IdeController::IdeController(Params
*p
)
60 // initialize the PIO interface addresses
62 pri_cmd_size
= BARSize
[0];
65 pri_ctrl_size
= BARSize
[1];
68 sec_cmd_size
= BARSize
[2];
71 sec_ctrl_size
= BARSize
[3];
73 // initialize the bus master interface (BMI) address to be configured
76 bmi_size
= BARSize
[4];
78 // zero out all of the registers
79 memset(bmi_regs
, 0, sizeof(bmi_regs
));
80 memset(pci_regs
, 0, sizeof(pci_regs
));
82 // setup initial values
83 *(uint32_t *)&pci_regs
[IDETIM
] = 0x80008000; // enable both channels
84 *(uint8_t *)&bmi_regs
[BMIS0
] = 0x60;
85 *(uint8_t *)&bmi_regs
[BMIS1
] = 0x60;
87 // reset all internal variables
90 memset(cmd_in_progress
, 0, sizeof(cmd_in_progress
));
92 // create the PIO and DMA interfaces
93 if (params()->host_bus
) {
94 pioInterface
= newPioInterface(name(), params()->hier
,
95 params()->host_bus
, this,
96 &IdeController::cacheAccess
);
98 dmaInterface
= new DMAInterface
<Bus
>(name() + ".dma",
100 params()->host_bus
, 1);
101 pioLatency
= params()->pio_latency
* params()->host_bus
->clockRatio
;
104 // setup the disks attached to controller
105 memset(disks
, 0, sizeof(IdeDisk
*) * 4);
107 if (params()->disks
.size() > 3)
108 panic("IDE controllers support a maximum of 4 devices attached!\n");
110 for (int i
= 0; i
< params()->disks
.size(); i
++) {
111 disks
[i
] = params()->disks
[i
];
112 disks
[i
]->setController(this, dmaInterface
);
116 IdeController::~IdeController()
118 for (int i
= 0; i
< 4; i
++)
128 IdeController::parseAddr(const Addr
&addr
, Addr
&offset
, bool &primary
,
133 if (addr
>= pri_cmd_addr
&& addr
< (pri_cmd_addr
+ pri_cmd_size
)) {
134 offset
-= pri_cmd_addr
;
135 type
= COMMAND_BLOCK
;
137 } else if (addr
>= pri_ctrl_addr
&&
138 addr
< (pri_ctrl_addr
+ pri_ctrl_size
)) {
139 offset
-= pri_ctrl_addr
;
140 type
= CONTROL_BLOCK
;
142 } else if (addr
>= sec_cmd_addr
&&
143 addr
< (sec_cmd_addr
+ sec_cmd_size
)) {
144 offset
-= sec_cmd_addr
;
145 type
= COMMAND_BLOCK
;
147 } else if (addr
>= sec_ctrl_addr
&&
148 addr
< (sec_ctrl_addr
+ sec_ctrl_size
)) {
149 offset
-= sec_ctrl_addr
;
150 type
= CONTROL_BLOCK
;
152 } else if (addr
>= bmi_addr
&& addr
< (bmi_addr
+ bmi_size
)) {
155 primary
= (offset
< BMIC1
) ? true : false;
157 panic("IDE controller access to invalid address: %#x\n", addr
);
162 IdeController::getDisk(bool primary
)
165 uint8_t *devBit
= &dev
[0];
174 assert(*devBit
== 0 || *devBit
== 1);
180 IdeController::getDisk(IdeDisk
*diskPtr
)
182 for (int i
= 0; i
< 4; i
++) {
183 if ((long)diskPtr
== (long)disks
[i
])
190 IdeController::isDiskSelected(IdeDisk
*diskPtr
)
192 for (int i
= 0; i
< 4; i
++) {
193 if ((long)diskPtr
== (long)disks
[i
]) {
194 // is disk is on primary or secondary channel
196 // is disk the master or slave
199 return (dev
[channel
] == devID
);
202 panic("Unable to find disk by pointer!!\n");
206 // Command completion
210 IdeController::setDmaComplete(IdeDisk
*disk
)
212 int diskNum
= getDisk(disk
);
215 panic("Unable to find disk based on pointer %#x\n", disk
);
218 // clear the start/stop bit in the command register
219 bmi_regs
[BMIC0
] &= ~SSBM
;
220 // clear the bus master active bit in the status register
221 bmi_regs
[BMIS0
] &= ~BMIDEA
;
222 // set the interrupt bit
223 bmi_regs
[BMIS0
] |= IDEINTS
;
225 // clear the start/stop bit in the command register
226 bmi_regs
[BMIC1
] &= ~SSBM
;
227 // clear the bus master active bit in the status register
228 bmi_regs
[BMIS1
] &= ~BMIDEA
;
229 // set the interrupt bit
230 bmi_regs
[BMIS1
] |= IDEINTS
;
235 // Bus timing and bus access functions
239 IdeController::cacheAccess(MemReqPtr
&req
)
241 // @todo Add more accurate timing to cache access
242 return curTick
+ pioLatency
;
246 // Read and write handling
250 IdeController::ReadConfig(int offset
, int size
, uint8_t *data
)
254 Addr origOffset
= offset
;
257 if (offset
< PCI_DEVICE_SPECIFIC
) {
258 PciDev::ReadConfig(offset
, size
, data
);
260 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
261 offset
-= PCI_IDE_TIMING
;
264 if ((offset
+ size
) > (IDETIM
+ 4))
265 panic("PCI read of IDETIM with invalid size\n");
266 } else if (offset
== PCI_SLAVE_TIMING
) {
267 offset
-= PCI_SLAVE_TIMING
;
270 if ((offset
+ size
) > (SIDETIM
+ 1))
271 panic("PCI read of SIDETIM with invalid size\n");
272 } else if (offset
== PCI_UDMA33_CTRL
) {
273 offset
-= PCI_UDMA33_CTRL
;
276 if ((offset
+ size
) > (UDMACTL
+ 1))
277 panic("PCI read of UDMACTL with invalid size\n");
278 } else if (offset
>= PCI_UDMA33_TIMING
&&
279 offset
< (PCI_UDMA33_TIMING
+ 2)) {
280 offset
-= PCI_UDMA33_TIMING
;
283 if ((offset
+ size
) > (UDMATIM
+ 2))
284 panic("PCI read of UDMATIM with invalid size\n");
286 panic("PCI read of unimplemented register: %x\n", offset
);
289 memcpy((void *)data
, (void *)&pci_regs
[offset
], size
);
292 DPRINTF(IdeCtrl
, "PCI read offset: %#x (%#x) size: %#x data: %#x\n",
293 origOffset
, offset
, size
,
294 (*(uint32_t *)data
) & (0xffffffff >> 8 * (4 - size
)));
298 IdeController::WriteConfig(int offset
, int size
, uint32_t data
)
300 DPRINTF(IdeCtrl
, "PCI write offset: %#x size: %#x data: %#x\n",
301 offset
, size
, data
& (0xffffffff >> 8 * (4 - size
)));
303 // do standard write stuff if in standard PCI space
304 if (offset
< PCI_DEVICE_SPECIFIC
) {
305 PciDev::WriteConfig(offset
, size
, data
);
307 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
308 offset
-= PCI_IDE_TIMING
;
311 if ((offset
+ size
) > (IDETIM
+ 4))
312 panic("PCI write to IDETIM with invalid size\n");
313 } else if (offset
== PCI_SLAVE_TIMING
) {
314 offset
-= PCI_SLAVE_TIMING
;
317 if ((offset
+ size
) > (SIDETIM
+ 1))
318 panic("PCI write to SIDETIM with invalid size\n");
319 } else if (offset
== PCI_UDMA33_CTRL
) {
320 offset
-= PCI_UDMA33_CTRL
;
323 if ((offset
+ size
) > (UDMACTL
+ 1))
324 panic("PCI write to UDMACTL with invalid size\n");
325 } else if (offset
>= PCI_UDMA33_TIMING
&&
326 offset
< (PCI_UDMA33_TIMING
+ 2)) {
327 offset
-= PCI_UDMA33_TIMING
;
330 if ((offset
+ size
) > (UDMATIM
+ 2))
331 panic("PCI write to UDMATIM with invalid size\n");
333 panic("PCI write to unimplemented register: %x\n", offset
);
336 memcpy((void *)&pci_regs
[offset
], (void *)&data
, size
);
339 // Catch the writes to specific PCI registers that have side affects
340 // (like updating the PIO ranges)
343 if (config
.data
[offset
] & PCI_CMD_IOSE
)
348 if (config
.data
[offset
] & PCI_CMD_BME
)
354 case PCI0_BASE_ADDR0
:
355 if (BARAddrs
[0] != 0) {
356 pri_cmd_addr
= BARAddrs
[0];
358 pioInterface
->addAddrRange(RangeSize(pri_cmd_addr
,
361 pri_cmd_addr
&= EV5::PAddrUncachedMask
;
365 case PCI0_BASE_ADDR1
:
366 if (BARAddrs
[1] != 0) {
367 pri_ctrl_addr
= BARAddrs
[1];
369 pioInterface
->addAddrRange(RangeSize(pri_ctrl_addr
,
372 pri_ctrl_addr
&= EV5::PAddrUncachedMask
;
376 case PCI0_BASE_ADDR2
:
377 if (BARAddrs
[2] != 0) {
378 sec_cmd_addr
= BARAddrs
[2];
380 pioInterface
->addAddrRange(RangeSize(sec_cmd_addr
,
383 sec_cmd_addr
&= EV5::PAddrUncachedMask
;
387 case PCI0_BASE_ADDR3
:
388 if (BARAddrs
[3] != 0) {
389 sec_ctrl_addr
= BARAddrs
[3];
391 pioInterface
->addAddrRange(RangeSize(sec_ctrl_addr
,
394 sec_ctrl_addr
&= EV5::PAddrUncachedMask
;
398 case PCI0_BASE_ADDR4
:
399 if (BARAddrs
[4] != 0) {
400 bmi_addr
= BARAddrs
[4];
402 pioInterface
->addAddrRange(RangeSize(bmi_addr
, bmi_size
));
404 bmi_addr
&= EV5::PAddrUncachedMask
;
411 IdeController::read(MemReqPtr
&req
, uint8_t *data
)
420 parseAddr(req
->paddr
, offset
, primary
, type
);
421 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
422 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
427 // sanity check the size (allows byte, word, or dword access)
428 if (req
->size
!= sizeof(uint8_t) && req
->size
!= sizeof(uint16_t) &&
429 req
->size
!= sizeof(uint32_t))
430 panic("IDE controller read of invalid size: %#x\n", req
->size
);
432 if (type
!= BMI_BLOCK
) {
433 assert(req
->size
!= sizeof(uint32_t));
435 disk
= getDisk(primary
);
437 disks
[disk
]->read(offset
, byte
, cmdBlk
, data
);
439 memcpy((void *)data
, &bmi_regs
[offset
], req
->size
);
442 DPRINTF(IdeCtrl
, "read from offset: %#x size: %#x data: %#x\n",
444 (*(uint32_t *)data
) & (0xffffffff >> 8 * (4 - req
->size
)));
450 IdeController::write(MemReqPtr
&req
, const uint8_t *data
)
459 parseAddr(req
->paddr
, offset
, primary
, type
);
460 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
461 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
463 DPRINTF(IdeCtrl
, "write from offset: %#x size: %#x data: %#x\n",
465 (*(uint32_t *)data
) & (0xffffffff >> 8 * (4 - req
->size
)));
467 uint8_t oldVal
, newVal
;
472 if (type
== BMI_BLOCK
&& !bm_enabled
)
475 if (type
!= BMI_BLOCK
) {
476 // shadow the dev bit
477 if (type
== COMMAND_BLOCK
&& offset
== IDE_SELECT_OFFSET
) {
478 uint8_t *devBit
= (primary
? &dev
[0] : &dev
[1]);
479 *devBit
= ((*data
& IDE_SELECT_DEV_BIT
) ? 1 : 0);
482 assert(req
->size
!= sizeof(uint32_t));
484 disk
= getDisk(primary
);
486 disks
[disk
]->write(offset
, byte
, cmdBlk
, data
);
489 // Bus master IDE command register
492 if (req
->size
!= sizeof(uint8_t))
493 panic("Invalid BMIC write size: %x\n", req
->size
);
495 // select the current disk based on DEV bit
496 disk
= getDisk(primary
);
498 oldVal
= bmi_regs
[offset
];
501 // if a DMA transfer is in progress, R/W control cannot change
503 if ((oldVal
& RWCON
) ^ (newVal
& RWCON
)) {
504 (oldVal
& RWCON
) ? newVal
|= RWCON
: newVal
&= ~RWCON
;
508 // see if the start/stop bit is being changed
509 if ((oldVal
& SSBM
) ^ (newVal
& SSBM
)) {
511 // stopping DMA transfer
512 DPRINTF(IdeCtrl
, "Stopping DMA transfer\n");
514 // clear the BMIDEA bit
515 bmi_regs
[offset
+ 0x2] &= ~BMIDEA
;
517 if (disks
[disk
] == NULL
)
518 panic("DMA stop for disk %d which does not exist\n",
521 // inform the disk of the DMA transfer abort
522 disks
[disk
]->abortDma();
524 // starting DMA transfer
525 DPRINTF(IdeCtrl
, "Starting DMA transfer\n");
527 // set the BMIDEA bit
528 bmi_regs
[offset
+ 0x2] |= BMIDEA
;
530 if (disks
[disk
] == NULL
)
531 panic("DMA start for disk %d which does not exist\n",
534 // inform the disk of the DMA transfer start
536 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP0
]);
538 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP1
]);
542 // update the register value
543 bmi_regs
[offset
] = newVal
;
546 // Bus master IDE status register
549 if (req
->size
!= sizeof(uint8_t))
550 panic("Invalid BMIS write size: %x\n", req
->size
);
552 oldVal
= bmi_regs
[offset
];
555 // the BMIDEA bit is RO
556 newVal
|= (oldVal
& BMIDEA
);
558 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
559 if ((oldVal
& IDEINTS
) && (newVal
& IDEINTS
))
560 newVal
&= ~IDEINTS
; // clear the interrupt?
562 (oldVal
& IDEINTS
) ? newVal
|= IDEINTS
: newVal
&= ~IDEINTS
;
564 if ((oldVal
& IDEDMAE
) && (newVal
& IDEDMAE
))
567 (oldVal
& IDEDMAE
) ? newVal
|= IDEDMAE
: newVal
&= ~IDEDMAE
;
569 bmi_regs
[offset
] = newVal
;
572 // Bus master IDE descriptor table pointer register
575 if (req
->size
!= sizeof(uint32_t))
576 panic("Invalid BMIDTP write size: %x\n", req
->size
);
578 *(uint32_t *)&bmi_regs
[offset
] = *(uint32_t *)data
& ~0x3;
582 if (req
->size
!= sizeof(uint8_t) &&
583 req
->size
!= sizeof(uint16_t) &&
584 req
->size
!= sizeof(uint32_t))
585 panic("IDE controller write of invalid write size: %x\n",
588 // do a default copy of data into the registers
589 memcpy((void *)&bmi_regs
[offset
], data
, req
->size
);
601 IdeController::serialize(std::ostream
&os
)
603 // Serialize the PciDev base class
604 PciDev::serialize(os
);
606 // Serialize register addresses and sizes
607 SERIALIZE_SCALAR(pri_cmd_addr
);
608 SERIALIZE_SCALAR(pri_cmd_size
);
609 SERIALIZE_SCALAR(pri_ctrl_addr
);
610 SERIALIZE_SCALAR(pri_ctrl_size
);
611 SERIALIZE_SCALAR(sec_cmd_addr
);
612 SERIALIZE_SCALAR(sec_cmd_size
);
613 SERIALIZE_SCALAR(sec_ctrl_addr
);
614 SERIALIZE_SCALAR(sec_ctrl_size
);
615 SERIALIZE_SCALAR(bmi_addr
);
616 SERIALIZE_SCALAR(bmi_size
);
618 // Serialize registers
619 SERIALIZE_ARRAY(bmi_regs
, 16);
620 SERIALIZE_ARRAY(dev
, 2);
621 SERIALIZE_ARRAY(pci_regs
, 8);
623 // Serialize internal state
624 SERIALIZE_SCALAR(io_enabled
);
625 SERIALIZE_SCALAR(bm_enabled
);
626 SERIALIZE_ARRAY(cmd_in_progress
, 4);
630 IdeController::unserialize(Checkpoint
*cp
, const std::string
§ion
)
632 // Unserialize the PciDev base class
633 PciDev::unserialize(cp
, section
);
635 // Unserialize register addresses and sizes
636 UNSERIALIZE_SCALAR(pri_cmd_addr
);
637 UNSERIALIZE_SCALAR(pri_cmd_size
);
638 UNSERIALIZE_SCALAR(pri_ctrl_addr
);
639 UNSERIALIZE_SCALAR(pri_ctrl_size
);
640 UNSERIALIZE_SCALAR(sec_cmd_addr
);
641 UNSERIALIZE_SCALAR(sec_cmd_size
);
642 UNSERIALIZE_SCALAR(sec_ctrl_addr
);
643 UNSERIALIZE_SCALAR(sec_ctrl_size
);
644 UNSERIALIZE_SCALAR(bmi_addr
);
645 UNSERIALIZE_SCALAR(bmi_size
);
647 // Unserialize registers
648 UNSERIALIZE_ARRAY(bmi_regs
, 16);
649 UNSERIALIZE_ARRAY(dev
, 2);
650 UNSERIALIZE_ARRAY(pci_regs
, 8);
652 // Unserialize internal state
653 UNSERIALIZE_SCALAR(io_enabled
);
654 UNSERIALIZE_SCALAR(bm_enabled
);
655 UNSERIALIZE_ARRAY(cmd_in_progress
, 4);
658 pioInterface
->addAddrRange(RangeSize(pri_cmd_addr
, pri_cmd_size
));
659 pioInterface
->addAddrRange(RangeSize(pri_ctrl_addr
, pri_ctrl_size
));
660 pioInterface
->addAddrRange(RangeSize(sec_cmd_addr
, sec_cmd_size
));
661 pioInterface
->addAddrRange(RangeSize(sec_ctrl_addr
, sec_ctrl_size
));
662 pioInterface
->addAddrRange(RangeSize(bmi_addr
, bmi_size
));
666 #ifndef DOXYGEN_SHOULD_SKIP_THIS
668 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
671 SimObjectVectorParam
<IdeDisk
*> disks
;
672 SimObjectParam
<MemoryController
*> mmu
;
673 SimObjectParam
<PciConfigAll
*> configspace
;
674 SimObjectParam
<PciConfigData
*> configdata
;
675 SimObjectParam
<Platform
*> platform
;
676 Param
<uint32_t> pci_bus
;
677 Param
<uint32_t> pci_dev
;
678 Param
<uint32_t> pci_func
;
679 SimObjectParam
<Bus
*> io_bus
;
680 Param
<Tick
> pio_latency
;
681 SimObjectParam
<HierParams
*> hier
;
683 END_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
685 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController
)
687 INIT_PARAM(addr
, "Device Address"),
688 INIT_PARAM(disks
, "IDE disks attached to this controller"),
689 INIT_PARAM(mmu
, "Memory controller"),
690 INIT_PARAM(configspace
, "PCI Configspace"),
691 INIT_PARAM(configdata
, "PCI Config data"),
692 INIT_PARAM(platform
, "Platform pointer"),
693 INIT_PARAM(pci_bus
, "PCI bus ID"),
694 INIT_PARAM(pci_dev
, "PCI device number"),
695 INIT_PARAM(pci_func
, "PCI function code"),
696 INIT_PARAM_DFLT(io_bus
, "Host bus to attach to", NULL
),
697 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
698 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
700 END_INIT_SIM_OBJECT_PARAMS(IdeController
)
702 CREATE_SIM_OBJECT(IdeController
)
704 IdeController::Params
*params
= new IdeController::Params
;
705 params
->name
= getInstanceName();
707 params
->configSpace
= configspace
;
708 params
->configData
= configdata
;
709 params
->plat
= platform
;
710 params
->busNum
= pci_bus
;
711 params
->deviceNum
= pci_dev
;
712 params
->functionNum
= pci_func
;
714 params
->disks
= disks
;
715 params
->host_bus
= io_bus
;
716 params
->pio_latency
= pio_latency
;
718 return new IdeController(params
);
721 REGISTER_SIM_OBJECT("IdeController", IdeController
)
723 #endif //DOXYGEN_SHOULD_SKIP_THIS