dev/ide_ctrl.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstddef>
  30 #include <cstdlib>
  31 #include <string>
  32 #include <vector>
  33
  34 #include "base/trace.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/dma.hh"
  37 #include "dev/ide_ctrl.hh"
  38 #include "dev/ide_disk.hh"
  39 #include "dev/pciconfigall.hh"
  40 #include "dev/pcireg.h"
  41 #include "dev/platform.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/dma_interface.hh"
  44 #include "mem/bus/pio_interface.hh"
  45 #include "mem/bus/pio_interface_impl.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "mem/functional_mem/physical_memory.hh"
  48 #include "sim/builder.hh"
  49 #include "sim/sim_object.hh"
  50
  51 using namespace std;
  52
  53 ////
  54 // Initialization and destruction
  55 ////
  56
  57 IdeController::IdeController(Params *p)
  58     : PciDev(p)
  59 {
  60     // initialize the PIO interface addresses
  61     pri_cmd_addr = 0;
  62     pri_cmd_size = BARSize[0];
  63
  64     pri_ctrl_addr = 0;
  65     pri_ctrl_size = BARSize[1];
  66
  67     sec_cmd_addr = 0;
  68     sec_cmd_size = BARSize[2];
  69
  70     sec_ctrl_addr = 0;
  71     sec_ctrl_size = BARSize[3];
  72
  73     // initialize the bus master interface (BMI) address to be configured
  74     // via PCI
  75     bmi_addr = 0;
  76     bmi_size = BARSize[4];
  77
  78     // zero out all of the registers
  79     memset(bmi_regs, 0, sizeof(bmi_regs));
  80     memset(pci_regs, 0, sizeof(pci_regs));
  81
  82     // setup initial values
  83     *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
  84     *(uint8_t *)&bmi_regs[BMIS0] = 0x60;
  85     *(uint8_t *)&bmi_regs[BMIS1] = 0x60;
  86
  87     // reset all internal variables
  88     io_enabled = false;
  89     bm_enabled = false;
  90     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
  91
  92     // create the PIO and DMA interfaces
  93     if (params()->host_bus) {
  94         pioInterface = newPioInterface(name(), params()->hier,
  95                                        params()->host_bus, this,
  96                                        &IdeController::cacheAccess);
  97
  98         dmaInterface = new DMAInterface<Bus>(name() + ".dma",
  99                                              params()->host_bus,
 100                                              params()->host_bus, 1,
 101                                              true);
 102         pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
 103     }
 104
 105     // setup the disks attached to controller
 106     memset(disks, 0, sizeof(IdeDisk *) * 4);
 107
 108     if (params()->disks.size() > 3)
 109         panic("IDE controllers support a maximum of 4 devices attached!\n");
 110
 111     for (int i = 0; i < params()->disks.size(); i++) {
 112         disks[i] = params()->disks[i];
 113         disks[i]->setController(this, dmaInterface);
 114     }
 115 }
 116
 117 IdeController::~IdeController()
 118 {
 119     for (int i = 0; i < 4; i++)
 120         if (disks[i])
 121             delete disks[i];
 122 }
 123
 124 ////
 125 // Utility functions
 126 ///
 127
 128 void
 129 IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
 130                          RegType_t &type)
 131 {
 132     offset = addr;
 133
 134     if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
 135         offset -= pri_cmd_addr;
 136         type = COMMAND_BLOCK;
 137         primary = true;
 138     } else if (addr >= pri_ctrl_addr &&
 139                addr < (pri_ctrl_addr + pri_ctrl_size)) {
 140         offset -= pri_ctrl_addr;
 141         type = CONTROL_BLOCK;
 142         primary = true;
 143     } else if (addr >= sec_cmd_addr &&
 144                addr < (sec_cmd_addr + sec_cmd_size)) {
 145         offset -= sec_cmd_addr;
 146         type = COMMAND_BLOCK;
 147         primary = false;
 148     } else if (addr >= sec_ctrl_addr &&
 149                addr < (sec_ctrl_addr + sec_ctrl_size)) {
 150         offset -= sec_ctrl_addr;
 151         type = CONTROL_BLOCK;
 152         primary = false;
 153     } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
 154         offset -= bmi_addr;
 155         type = BMI_BLOCK;
 156         primary = (offset < BMIC1) ? true : false;
 157     } else {
 158         panic("IDE controller access to invalid address: %#x\n", addr);
 159     }
 160 }
 161
 162 int
 163 IdeController::getDisk(bool primary)
 164 {
 165     int disk = 0;
 166     uint8_t *devBit = &dev[0];
 167
 168     if (!primary) {
 169         disk += 2;
 170         devBit = &dev[1];
 171     }
 172
 173     disk += *devBit;
 174
 175     assert(*devBit == 0 || *devBit == 1);
 176
 177     return disk;
 178 }
 179
 180 int
 181 IdeController::getDisk(IdeDisk *diskPtr)
 182 {
 183     for (int i = 0; i < 4; i++) {
 184         if ((long)diskPtr == (long)disks[i])
 185             return i;
 186     }
 187     return -1;
 188 }
 189
 190 bool
 191 IdeController::isDiskSelected(IdeDisk *diskPtr)
 192 {
 193     for (int i = 0; i < 4; i++) {
 194         if ((long)diskPtr == (long)disks[i]) {
 195             // is disk is on primary or secondary channel
 196             int channel = i/2;
 197             // is disk the master or slave
 198             int devID = i%2;
 199
 200             return (dev[channel] == devID);
 201         }
 202     }
 203     panic("Unable to find disk by pointer!!\n");
 204 }
 205
 206 ////
 207 // Command completion
 208 ////
 209
 210 void
 211 IdeController::setDmaComplete(IdeDisk *disk)
 212 {
 213     int diskNum = getDisk(disk);
 214
 215     if (diskNum < 0)
 216         panic("Unable to find disk based on pointer %#x\n", disk);
 217
 218     if (diskNum < 2) {
 219         // clear the start/stop bit in the command register
 220         bmi_regs[BMIC0] &= ~SSBM;
 221         // clear the bus master active bit in the status register
 222         bmi_regs[BMIS0] &= ~BMIDEA;
 223         // set the interrupt bit
 224         bmi_regs[BMIS0] |= IDEINTS;
 225     } else {
 226         // clear the start/stop bit in the command register
 227         bmi_regs[BMIC1] &= ~SSBM;
 228         // clear the bus master active bit in the status register
 229         bmi_regs[BMIS1] &= ~BMIDEA;
 230         // set the interrupt bit
 231         bmi_regs[BMIS1] |= IDEINTS;
 232     }
 233 }
 234
 235 ////
 236 // Bus timing and bus access functions
 237 ////
 238
 239 Tick
 240 IdeController::cacheAccess(MemReqPtr &req)
 241 {
 242     // @todo Add more accurate timing to cache access
 243     return curTick + pioLatency;
 244 }
 245
 246 ////
 247 // Read and write handling
 248 ////
 249
 250 void
 251 IdeController::ReadConfig(int offset, int size, uint8_t *data)
 252 {
 253
 254 #if TRACING_ON
 255     Addr origOffset = offset;
 256 #endif
 257
 258     if (offset < PCI_DEVICE_SPECIFIC) {
 259         PciDev::ReadConfig(offset, size, data);
 260     } else {
 261         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 262             offset -= PCI_IDE_TIMING;
 263             offset += IDETIM;
 264
 265             if ((offset + size) > (IDETIM + 4))
 266                 panic("PCI read of IDETIM with invalid size\n");
 267         } else if (offset == PCI_SLAVE_TIMING) {
 268             offset -= PCI_SLAVE_TIMING;
 269             offset += SIDETIM;
 270
 271             if ((offset + size) > (SIDETIM + 1))
 272                 panic("PCI read of SIDETIM with invalid size\n");
 273         } else if (offset == PCI_UDMA33_CTRL) {
 274             offset -= PCI_UDMA33_CTRL;
 275             offset += UDMACTL;
 276
 277             if ((offset + size) > (UDMACTL + 1))
 278                 panic("PCI read of UDMACTL with invalid size\n");
 279         } else if (offset >= PCI_UDMA33_TIMING &&
 280                    offset < (PCI_UDMA33_TIMING + 2)) {
 281             offset -= PCI_UDMA33_TIMING;
 282             offset += UDMATIM;
 283
 284             if ((offset + size) > (UDMATIM + 2))
 285                 panic("PCI read of UDMATIM with invalid size\n");
 286         } else {
 287             panic("PCI read of unimplemented register: %x\n", offset);
 288         }
 289
 290         memcpy((void *)data, (void *)&pci_regs[offset], size);
 291     }
 292
 293     DPRINTF(IdeCtrl, "PCI read offset: %#x (%#x) size: %#x data: %#x\n",
 294             origOffset, offset, size,
 295             (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - size)));
 296 }
 297
 298 void
 299 IdeController::WriteConfig(int offset, int size, uint32_t data)
 300 {
 301     DPRINTF(IdeCtrl, "PCI write offset: %#x size: %#x data: %#x\n",
 302             offset, size, data & (0xffffffff >> 8 * (4 - size)));
 303
 304     // do standard write stuff if in standard PCI space
 305     if (offset < PCI_DEVICE_SPECIFIC) {
 306         PciDev::WriteConfig(offset, size, data);
 307     } else {
 308         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 309             offset -= PCI_IDE_TIMING;
 310             offset += IDETIM;
 311
 312             if ((offset + size) > (IDETIM + 4))
 313                 panic("PCI write to IDETIM with invalid size\n");
 314         } else if (offset == PCI_SLAVE_TIMING) {
 315             offset -= PCI_SLAVE_TIMING;
 316             offset += SIDETIM;
 317
 318             if ((offset + size) > (SIDETIM + 1))
 319                 panic("PCI write to SIDETIM with invalid size\n");
 320         } else if (offset == PCI_UDMA33_CTRL) {
 321             offset -= PCI_UDMA33_CTRL;
 322             offset += UDMACTL;
 323
 324             if ((offset + size) > (UDMACTL + 1))
 325                 panic("PCI write to UDMACTL with invalid size\n");
 326         } else if (offset >= PCI_UDMA33_TIMING &&
 327                    offset < (PCI_UDMA33_TIMING + 2)) {
 328             offset -= PCI_UDMA33_TIMING;
 329             offset += UDMATIM;
 330
 331             if ((offset + size) > (UDMATIM + 2))
 332                 panic("PCI write to UDMATIM with invalid size\n");
 333         } else {
 334             panic("PCI write to unimplemented register: %x\n", offset);
 335         }
 336
 337         memcpy((void *)&pci_regs[offset], (void *)&data, size);
 338     }
 339
 340     // Catch the writes to specific PCI registers that have side affects
 341     // (like updating the PIO ranges)
 342     switch (offset) {
 343       case PCI_COMMAND:
 344         if (config.data[offset] & PCI_CMD_IOSE)
 345             io_enabled = true;
 346         else
 347             io_enabled = false;
 348
 349         if (config.data[offset] & PCI_CMD_BME)
 350             bm_enabled = true;
 351         else
 352             bm_enabled = false;
 353         break;
 354
 355       case PCI0_BASE_ADDR0:
 356         if (BARAddrs[0] != 0) {
 357             pri_cmd_addr = BARAddrs[0];
 358             if (pioInterface)
 359                 pioInterface->addAddrRange(RangeSize(pri_cmd_addr,
 360                                                      pri_cmd_size));
 361
 362             pri_cmd_addr &= EV5::PAddrUncachedMask;
 363         }
 364         break;
 365
 366       case PCI0_BASE_ADDR1:
 367         if (BARAddrs[1] != 0) {
 368             pri_ctrl_addr = BARAddrs[1];
 369             if (pioInterface)
 370                 pioInterface->addAddrRange(RangeSize(pri_ctrl_addr,
 371                                                      pri_ctrl_size));
 372
 373             pri_ctrl_addr &= EV5::PAddrUncachedMask;
 374         }
 375         break;
 376
 377       case PCI0_BASE_ADDR2:
 378         if (BARAddrs[2] != 0) {
 379             sec_cmd_addr = BARAddrs[2];
 380             if (pioInterface)
 381                 pioInterface->addAddrRange(RangeSize(sec_cmd_addr,
 382                                                      sec_cmd_size));
 383
 384             sec_cmd_addr &= EV5::PAddrUncachedMask;
 385         }
 386         break;
 387
 388       case PCI0_BASE_ADDR3:
 389         if (BARAddrs[3] != 0) {
 390             sec_ctrl_addr = BARAddrs[3];
 391             if (pioInterface)
 392                 pioInterface->addAddrRange(RangeSize(sec_ctrl_addr,
 393                                                      sec_ctrl_size));
 394
 395             sec_ctrl_addr &= EV5::PAddrUncachedMask;
 396         }
 397         break;
 398
 399       case PCI0_BASE_ADDR4:
 400         if (BARAddrs[4] != 0) {
 401             bmi_addr = BARAddrs[4];
 402             if (pioInterface)
 403                 pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
 404
 405             bmi_addr &= EV5::PAddrUncachedMask;
 406         }
 407         break;
 408     }
 409 }
 410
 411 Fault
 412 IdeController::read(MemReqPtr &req, uint8_t *data)
 413 {
 414     Addr offset;
 415     bool primary;
 416     bool byte;
 417     bool cmdBlk;
 418     RegType_t type;
 419     int disk;
 420
 421     parseAddr(req->paddr, offset, primary, type);
 422     byte = (req->size == sizeof(uint8_t)) ? true : false;
 423     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 424
 425     if (!io_enabled)
 426         return No_Fault;
 427
 428     // sanity check the size (allows byte, word, or dword access)
 429     if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
 430         req->size != sizeof(uint32_t))
 431         panic("IDE controller read of invalid size: %#x\n", req->size);
 432
 433     if (type != BMI_BLOCK) {
 434         assert(req->size != sizeof(uint32_t));
 435
 436         disk = getDisk(primary);
 437         if (disks[disk])
 438             disks[disk]->read(offset, byte, cmdBlk, data);
 439     } else {
 440         memcpy((void *)data, &bmi_regs[offset], req->size);
 441     }
 442
 443     DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
 444             offset, req->size,
 445             (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
 446
 447     return No_Fault;
 448 }
 449
 450 Fault
 451 IdeController::write(MemReqPtr &req, const uint8_t *data)
 452 {
 453     Addr offset;
 454     bool primary;
 455     bool byte;
 456     bool cmdBlk;
 457     RegType_t type;
 458     int disk;
 459
 460     parseAddr(req->paddr, offset, primary, type);
 461     byte = (req->size == sizeof(uint8_t)) ? true : false;
 462     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 463
 464     DPRINTF(IdeCtrl, "write from offset: %#x size: %#x data: %#x\n",
 465             offset, req->size,
 466             (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
 467
 468     uint8_t oldVal, newVal;
 469
 470     if (!io_enabled)
 471         return No_Fault;
 472
 473     if (type == BMI_BLOCK && !bm_enabled)
 474         return No_Fault;
 475
 476     if (type != BMI_BLOCK) {
 477         // shadow the dev bit
 478         if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
 479             uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
 480             *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
 481         }
 482
 483         assert(req->size != sizeof(uint32_t));
 484
 485         disk = getDisk(primary);
 486         if (disks[disk])
 487             disks[disk]->write(offset, byte, cmdBlk, data);
 488     } else {
 489         switch (offset) {
 490             // Bus master IDE command register
 491           case BMIC1:
 492           case BMIC0:
 493             if (req->size != sizeof(uint8_t))
 494                 panic("Invalid BMIC write size: %x\n", req->size);
 495
 496             // select the current disk based on DEV bit
 497             disk = getDisk(primary);
 498
 499             oldVal = bmi_regs[offset];
 500             newVal = *data;
 501
 502             // if a DMA transfer is in progress, R/W control cannot change
 503             if (oldVal & SSBM) {
 504                 if ((oldVal & RWCON) ^ (newVal & RWCON)) {
 505                     (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
 506                 }
 507             }
 508
 509             // see if the start/stop bit is being changed
 510             if ((oldVal & SSBM) ^ (newVal & SSBM)) {
 511                 if (oldVal & SSBM) {
 512                     // stopping DMA transfer
 513                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 514
 515                     // clear the BMIDEA bit
 516                     bmi_regs[offset + 0x2] &= ~BMIDEA;
 517
 518                     if (disks[disk] == NULL)
 519                         panic("DMA stop for disk %d which does not exist\n",
 520                               disk);
 521
 522                     // inform the disk of the DMA transfer abort
 523                     disks[disk]->abortDma();
 524                 } else {
 525                     // starting DMA transfer
 526                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 527
 528                     // set the BMIDEA bit
 529                     bmi_regs[offset + 0x2] |= BMIDEA;
 530
 531                     if (disks[disk] == NULL)
 532                         panic("DMA start for disk %d which does not exist\n",
 533                               disk);
 534
 535                     // inform the disk of the DMA transfer start
 536                     if (primary)
 537                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
 538                     else
 539                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
 540                 }
 541             }
 542
 543             // update the register value
 544             bmi_regs[offset] = newVal;
 545             break;
 546
 547             // Bus master IDE status register
 548           case BMIS0:
 549           case BMIS1:
 550             if (req->size != sizeof(uint8_t))
 551                 panic("Invalid BMIS write size: %x\n", req->size);
 552
 553             oldVal = bmi_regs[offset];
 554             newVal = *data;
 555
 556             // the BMIDEA bit is RO
 557             newVal |= (oldVal & BMIDEA);
 558
 559             // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
 560             if ((oldVal & IDEINTS) && (newVal & IDEINTS))
 561                 newVal &= ~IDEINTS; // clear the interrupt?
 562             else
 563                 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
 564
 565             if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
 566                 newVal &= ~IDEDMAE;
 567             else
 568                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 569
 570             bmi_regs[offset] = newVal;
 571             break;
 572
 573             // Bus master IDE descriptor table pointer register
 574           case BMIDTP0:
 575           case BMIDTP1:
 576             if (req->size != sizeof(uint32_t))
 577                 panic("Invalid BMIDTP write size: %x\n", req->size);
 578
 579             *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
 580             break;
 581
 582           default:
 583             if (req->size != sizeof(uint8_t) &&
 584                 req->size != sizeof(uint16_t) &&
 585                 req->size != sizeof(uint32_t))
 586                 panic("IDE controller write of invalid write size: %x\n",
 587                       req->size);
 588
 589             // do a default copy of data into the registers
 590             memcpy((void *)&bmi_regs[offset], data, req->size);
 591         }
 592     }
 593
 594     return No_Fault;
 595 }
 596
 597 ////
 598 // Serialization
 599 ////
 600
 601 void
 602 IdeController::serialize(std::ostream &os)
 603 {
 604     // Serialize the PciDev base class
 605     PciDev::serialize(os);
 606
 607     // Serialize register addresses and sizes
 608     SERIALIZE_SCALAR(pri_cmd_addr);
 609     SERIALIZE_SCALAR(pri_cmd_size);
 610     SERIALIZE_SCALAR(pri_ctrl_addr);
 611     SERIALIZE_SCALAR(pri_ctrl_size);
 612     SERIALIZE_SCALAR(sec_cmd_addr);
 613     SERIALIZE_SCALAR(sec_cmd_size);
 614     SERIALIZE_SCALAR(sec_ctrl_addr);
 615     SERIALIZE_SCALAR(sec_ctrl_size);
 616     SERIALIZE_SCALAR(bmi_addr);
 617     SERIALIZE_SCALAR(bmi_size);
 618
 619     // Serialize registers
 620     SERIALIZE_ARRAY(bmi_regs, 16);
 621     SERIALIZE_ARRAY(dev, 2);
 622     SERIALIZE_ARRAY(pci_regs, 8);
 623
 624     // Serialize internal state
 625     SERIALIZE_SCALAR(io_enabled);
 626     SERIALIZE_SCALAR(bm_enabled);
 627     SERIALIZE_ARRAY(cmd_in_progress, 4);
 628 }
 629
 630 void
 631 IdeController::unserialize(Checkpoint *cp, const std::string &section)
 632 {
 633     // Unserialize the PciDev base class
 634     PciDev::unserialize(cp, section);
 635
 636     // Unserialize register addresses and sizes
 637     UNSERIALIZE_SCALAR(pri_cmd_addr);
 638     UNSERIALIZE_SCALAR(pri_cmd_size);
 639     UNSERIALIZE_SCALAR(pri_ctrl_addr);
 640     UNSERIALIZE_SCALAR(pri_ctrl_size);
 641     UNSERIALIZE_SCALAR(sec_cmd_addr);
 642     UNSERIALIZE_SCALAR(sec_cmd_size);
 643     UNSERIALIZE_SCALAR(sec_ctrl_addr);
 644     UNSERIALIZE_SCALAR(sec_ctrl_size);
 645     UNSERIALIZE_SCALAR(bmi_addr);
 646     UNSERIALIZE_SCALAR(bmi_size);
 647
 648     // Unserialize registers
 649     UNSERIALIZE_ARRAY(bmi_regs, 16);
 650     UNSERIALIZE_ARRAY(dev, 2);
 651     UNSERIALIZE_ARRAY(pci_regs, 8);
 652
 653     // Unserialize internal state
 654     UNSERIALIZE_SCALAR(io_enabled);
 655     UNSERIALIZE_SCALAR(bm_enabled);
 656     UNSERIALIZE_ARRAY(cmd_in_progress, 4);
 657
 658     if (pioInterface) {
 659         pioInterface->addAddrRange(RangeSize(pri_cmd_addr, pri_cmd_size));
 660         pioInterface->addAddrRange(RangeSize(pri_ctrl_addr, pri_ctrl_size));
 661         pioInterface->addAddrRange(RangeSize(sec_cmd_addr, sec_cmd_size));
 662         pioInterface->addAddrRange(RangeSize(sec_ctrl_addr, sec_ctrl_size));
 663         pioInterface->addAddrRange(RangeSize(bmi_addr, bmi_size));
 664    }
 665 }
 666
 667 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 668
 669 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 670
 671     Param<Addr> addr;
 672     SimObjectVectorParam<IdeDisk *> disks;
 673     SimObjectParam<MemoryController *> mmu;
 674     SimObjectParam<PciConfigAll *> configspace;
 675     SimObjectParam<PciConfigData *> configdata;
 676     SimObjectParam<Platform *> platform;
 677     Param<uint32_t> pci_bus;
 678     Param<uint32_t> pci_dev;
 679     Param<uint32_t> pci_func;
 680     SimObjectParam<Bus *> io_bus;
 681     Param<Tick> pio_latency;
 682     SimObjectParam<HierParams *> hier;
 683
 684 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 685
 686 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 687
 688     INIT_PARAM(addr, "Device Address"),
 689     INIT_PARAM(disks, "IDE disks attached to this controller"),
 690     INIT_PARAM(mmu, "Memory controller"),
 691     INIT_PARAM(configspace, "PCI Configspace"),
 692     INIT_PARAM(configdata, "PCI Config data"),
 693     INIT_PARAM(platform, "Platform pointer"),
 694     INIT_PARAM(pci_bus, "PCI bus ID"),
 695     INIT_PARAM(pci_dev, "PCI device number"),
 696     INIT_PARAM(pci_func, "PCI function code"),
 697     INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
 698     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 699     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 700
 701 END_INIT_SIM_OBJECT_PARAMS(IdeController)
 702
 703 CREATE_SIM_OBJECT(IdeController)
 704 {
 705     IdeController::Params *params = new IdeController::Params;
 706     params->name = getInstanceName();
 707     params->mmu = mmu;
 708     params->configSpace = configspace;
 709     params->configData = configdata;
 710     params->plat = platform;
 711     params->busNum = pci_bus;
 712     params->deviceNum = pci_dev;
 713     params->functionNum = pci_func;
 714
 715     params->disks = disks;
 716     params->host_bus = io_bus;
 717     params->pio_latency = pio_latency;
 718     params->hier = hier;
 719     return new IdeController(params);
 720 }
 721
 722 REGISTER_SIM_OBJECT("IdeController", IdeController)
 723
 724 #endif //DOXYGEN_SHOULD_SKIP_THIS